Lines Matching refs:clock_set_target_val
90 clock_set_target_val(USB_HSIC_CLK_ROOT, target); in enable_usboh3_clk()
541 clock_set_target_val(I2C1_CLK_ROOT + i2c_num, target); in enable_i2c_clk()
565 clock_set_target_val(USDHC1_CLK_ROOT, target); in init_clk_esdhc()
570 clock_set_target_val(USDHC2_CLK_ROOT, target); in init_clk_esdhc()
575 clock_set_target_val(USDHC3_CLK_ROOT, target); in init_clk_esdhc()
600 clock_set_target_val(UART1_CLK_ROOT, target); in init_clk_uart()
605 clock_set_target_val(UART2_CLK_ROOT, target); in init_clk_uart()
610 clock_set_target_val(UART3_CLK_ROOT, target); in init_clk_uart()
615 clock_set_target_val(UART4_CLK_ROOT, target); in init_clk_uart()
620 clock_set_target_val(UART5_CLK_ROOT, target); in init_clk_uart()
625 clock_set_target_val(UART6_CLK_ROOT, target); in init_clk_uart()
630 clock_set_target_val(UART7_CLK_ROOT, target); in init_clk_uart()
653 clock_set_target_val(EIM_CLK_ROOT, target); in init_clk_weim()
673 clock_set_target_val(ECSPI1_CLK_ROOT, target); in init_clk_ecspi()
678 clock_set_target_val(ECSPI2_CLK_ROOT, target); in init_clk_ecspi()
683 clock_set_target_val(ECSPI3_CLK_ROOT, target); in init_clk_ecspi()
688 clock_set_target_val(ECSPI4_CLK_ROOT, target); in init_clk_ecspi()
711 clock_set_target_val(WDOG_CLK_ROOT, target); in init_clk_wdog()
732 clock_set_target_val(EPDC_PIXEL_CLK_ROOT, target); in init_clk_epdc()
864 clock_set_target_val(QSPI_CLK_ROOT, target); in set_clk_qspi()
884 clock_set_target_val(NAND_CLK_ROOT, target); in set_clk_nand()
952 clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, target); in mxs_set_lcdclk()
993 clock_set_target_val(ENET_AXI_CLK_ROOT, target); in set_clk_enet()
998 clock_set_target_val(ENET1_REF_CLK_ROOT, target); in set_clk_enet()
1003 clock_set_target_val(ENET1_TIME_CLK_ROOT, target); in set_clk_enet()
1008 clock_set_target_val(ENET2_REF_CLK_ROOT, target); in set_clk_enet()
1013 clock_set_target_val(ENET2_TIME_CLK_ROOT, target); in set_clk_enet()
1020 clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target); in set_clk_enet()