86 		target = CLK_ROOT_ON |  in enable_usboh3_clk()
537 		target = CLK_ROOT_ON |  in enable_i2c_clk()
562 	target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |  in init_clk_esdhc()
567 	target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |  in init_clk_esdhc()
572 	target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |  in init_clk_esdhc()
597 	target = CLK_ROOT_ON | UART1_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_uart()
602 	target = CLK_ROOT_ON | UART2_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_uart()
607 	target = CLK_ROOT_ON | UART3_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_uart()
612 	target = CLK_ROOT_ON | UART4_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_uart()
617 	target = CLK_ROOT_ON | UART5_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_uart()
622 	target = CLK_ROOT_ON | UART6_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_uart()
627 	target = CLK_ROOT_ON | UART7_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_uart()
650 	target = CLK_ROOT_ON | EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |  in init_clk_weim()
670 	target = CLK_ROOT_ON | ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |  in init_clk_ecspi()
675 	target = CLK_ROOT_ON | ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |  in init_clk_ecspi()
680 	target = CLK_ROOT_ON | ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |  in init_clk_ecspi()
685 	target = CLK_ROOT_ON | ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |  in init_clk_ecspi()
708 	target = CLK_ROOT_ON | WDOG_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_wdog()
729 	target = CLK_ROOT_ON | EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |  in init_clk_epdc()
861 	target = CLK_ROOT_ON | QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |  in set_clk_qspi()
881 	target = CLK_ROOT_ON | NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK |  in set_clk_nand()
950 	target = CLK_ROOT_ON | LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK |  in mxs_set_lcdclk()
990 	target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |  in set_clk_enet()
995 	target = CLK_ROOT_ON | enet1_ref |  in set_clk_enet()
1000 	target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |  in set_clk_enet()
1005 	target = CLK_ROOT_ON | enet2_ref |  in set_clk_enet()
1010 	target = CLK_ROOT_ON | ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |  in set_clk_enet()
1016 	target = CLK_ROOT_ON |  in set_clk_enet()