Lines Matching defs:exynos5_clock
516 struct exynos5_clock { struct
517 unsigned int apll_lock;
518 unsigned char res1[0xfc];
519 unsigned int apll_con0;
520 unsigned int apll_con1;
521 unsigned char res2[0xf8];
522 unsigned int src_cpu;
523 unsigned char res3[0x1fc];
524 unsigned int mux_stat_cpu;
525 unsigned char res4[0xfc];
526 unsigned int div_cpu0;
527 unsigned int div_cpu1;
528 unsigned char res5[0xf8];
529 unsigned int div_stat_cpu0;
530 unsigned int div_stat_cpu1;
531 unsigned char res6[0x1f8];
532 unsigned int gate_sclk_cpu;
533 unsigned char res7[0x1fc];
534 unsigned int clkout_cmu_cpu;
535 unsigned int clkout_cmu_cpu_div_stat;
536 unsigned char res8[0x5f8];
537 unsigned int armclk_stopctrl;
538 unsigned char res9[0x0c];
539 unsigned int parityfail_status;
540 unsigned int parityfail_clear;
541 unsigned char res10[0x8];
542 unsigned int pwr_ctrl;
543 unsigned int pwr_ctr2;
544 unsigned char res11[0xd8];
545 unsigned int apll_con0_l8;
546 unsigned int apll_con0_l7;
547 unsigned int apll_con0_l6;
548 unsigned int apll_con0_l5;
549 unsigned int apll_con0_l4;
550 unsigned int apll_con0_l3;
551 unsigned int apll_con0_l2;
552 unsigned int apll_con0_l1;
553 unsigned int iem_control;
554 unsigned char res12[0xdc];
555 unsigned int apll_con1_l8;
556 unsigned int apll_con1_l7;
557 unsigned int apll_con1_l6;
558 unsigned int apll_con1_l5;
559 unsigned int apll_con1_l4;
560 unsigned int apll_con1_l3;
561 unsigned int apll_con1_l2;
562 unsigned int apll_con1_l1;
563 unsigned char res13[0xe0];
564 unsigned int div_iem_l8;
565 unsigned int div_iem_l7;
566 unsigned int div_iem_l6;
567 unsigned int div_iem_l5;
568 unsigned int div_iem_l4;
569 unsigned int div_iem_l3;
570 unsigned int div_iem_l2;
571 unsigned int div_iem_l1;
572 unsigned char res14[0x2ce0];
573 unsigned int mpll_lock;
574 unsigned char res15[0xfc];
575 unsigned int mpll_con0;
576 unsigned int mpll_con1;
577 unsigned char res16[0xf8];
578 unsigned int src_core0;
579 unsigned int src_core1;
580 unsigned char res17[0xf8];
581 unsigned int src_mask_core;
582 unsigned char res18[0x100];
583 unsigned int mux_stat_core1;
584 unsigned char res19[0xf8];
585 unsigned int div_core0;
586 unsigned int div_core1;
587 unsigned int div_sysrgt;
588 unsigned char res20[0xf4];
589 unsigned int div_stat_core0;
590 unsigned int div_stat_core1;
591 unsigned int div_stat_sysrgt;
592 unsigned char res21[0x2f4];
593 unsigned int gate_ip_core;
594 unsigned int gate_ip_sysrgt;
595 unsigned char res22[0x8];
596 unsigned int c2c_monitor;
597 unsigned char res23[0xec];
598 unsigned int clkout_cmu_core;
599 unsigned int clkout_cmu_core_div_stat;
600 unsigned char res24[0x5f8];
601 unsigned int dcgidx_map0;
602 unsigned int dcgidx_map1;
603 unsigned int dcgidx_map2;
604 unsigned char res25[0x14];
605 unsigned int dcgperf_map0;
606 unsigned int dcgperf_map1;
607 unsigned char res26[0x18];
608 unsigned int dvcidx_map;
609 unsigned char res27[0x1c];
610 unsigned int freq_cpu;
611 unsigned int freq_dpm;
612 unsigned char res28[0x18];
613 unsigned int dvsemclk_en;
614 unsigned int maxperf;
615 unsigned char res29[0xf78];
616 unsigned int c2c_config;
617 unsigned char res30[0x24fc];
618 unsigned int div_acp;
619 unsigned char res31[0xfc];
620 unsigned int div_stat_acp;
621 unsigned char res32[0x1fc];
622 unsigned int gate_ip_acp;
623 unsigned char res33[0xfc];
624 unsigned int div_syslft;
625 unsigned char res34[0xc];
626 unsigned int div_stat_syslft;
627 unsigned char res35[0x1c];
628 unsigned int gate_ip_syslft;
629 unsigned char res36[0xcc];
630 unsigned int clkout_cmu_acp;
631 unsigned int clkout_cmu_acp_div_stat;
632 unsigned char res37[0x8];
633 unsigned int ufmc_config;
634 unsigned char res38[0x38ec];
635 unsigned int div_isp0;
636 unsigned int div_isp1;
637 unsigned int div_isp2;
638 unsigned char res39[0xf4];
639 unsigned int div_stat_isp0;
640 unsigned int div_stat_isp1;
641 unsigned int div_stat_isp2;
642 unsigned char res40[0x3f4];
643 unsigned int gate_ip_isp0;
644 unsigned int gate_ip_isp1;
645 unsigned char res41[0xf8];
646 unsigned int gate_sclk_isp;
647 unsigned char res42[0xc];
648 unsigned int mcuisp_pwr_ctrl;
649 unsigned char res43[0xec];
650 unsigned int clkout_cmu_isp;
651 unsigned int clkout_cmu_isp_div_stat;
652 unsigned char res44[0x3618];
653 unsigned int cpll_lock;
654 unsigned char res45[0xc];
655 unsigned int epll_lock;
656 unsigned char res46[0xc];
657 unsigned int vpll_lock;
658 unsigned char res47[0xc];
659 unsigned int gpll_lock;
660 unsigned char res48[0xcc];
661 unsigned int cpll_con0;
662 unsigned int cpll_con1;
663 unsigned char res49[0x8];
664 unsigned int epll_con0;
665 unsigned int epll_con1;
666 unsigned int epll_con2;
667 unsigned char res50[0x4];
668 unsigned int vpll_con0;
669 unsigned int vpll_con1;
670 unsigned int vpll_con2;
671 unsigned char res51[0x4];
672 unsigned int gpll_con0;
673 unsigned int gpll_con1;
674 unsigned char res52[0xb8];
675 unsigned int src_top0;
676 unsigned int src_top1;
677 unsigned int src_top2;
678 unsigned int src_top3;
679 unsigned int src_gscl;
680 unsigned char res53[0x8];
681 unsigned int src_disp1_0;
682 unsigned char res54[0x10];
683 unsigned int src_mau;
684 unsigned int src_fsys;
685 unsigned int src_gen;
686 unsigned char res55[0x4];
687 unsigned int src_peric0;
688 unsigned int src_peric1;
689 unsigned char res56[0x18];
690 unsigned int sclk_src_isp;
691 unsigned char res57[0x9c];
692 unsigned int src_mask_top;
693 unsigned char res58[0xc];
694 unsigned int src_mask_gscl;
695 unsigned char res59[0x8];
696 unsigned int src_mask_disp1_0;
697 unsigned char res60[0x4];
698 unsigned int src_mask_mau;
699 unsigned char res61[0x8];
700 unsigned int src_mask_fsys;
701 unsigned int src_mask_gen;
702 unsigned char res62[0x8];
703 unsigned int src_mask_peric0;
704 unsigned int src_mask_peric1;
705 unsigned char res63[0x18];
706 unsigned int src_mask_isp;
707 unsigned char res67[0x9c];
708 unsigned int mux_stat_top0;
709 unsigned int mux_stat_top1;
710 unsigned int mux_stat_top2;
711 unsigned int mux_stat_top3;
712 unsigned char res68[0xf0];
713 unsigned int div_top0;
714 unsigned int div_top1;
715 unsigned char res69[0x8];
716 unsigned int div_gscl;
717 unsigned char res70[0x8];
718 unsigned int div_disp1_0;
719 unsigned char res71[0xc];
720 unsigned int div_gen;
721 unsigned char res72[0x4];
722 unsigned int div_mau;
723 unsigned int div_fsys0;
724 unsigned int div_fsys1;
725 unsigned int div_fsys2;
726 unsigned char res73[0x4];
727 unsigned int div_peric0;
728 unsigned int div_peric1;
729 unsigned int div_peric2;
730 unsigned int div_peric3;
731 unsigned int div_peric4;
732 unsigned int div_peric5;
733 unsigned char res74[0x10];
734 unsigned int sclk_div_isp;
735 unsigned char res75[0xc];
736 unsigned int div2_ratio0;
737 unsigned int div2_ratio1;
738 unsigned char res76[0x8];
739 unsigned int div4_ratio;
740 unsigned char res77[0x6c];
741 unsigned int div_stat_top0;
742 unsigned int div_stat_top1;
743 unsigned char res78[0x8];
744 unsigned int div_stat_gscl;
745 unsigned char res79[0x8];
746 unsigned int div_stat_disp1_0;
747 unsigned char res80[0xc];
748 unsigned int div_stat_gen;
749 unsigned char res81[0x4];
750 unsigned int div_stat_mau;
751 unsigned int div_stat_fsys0;
752 unsigned int div_stat_fsys1;
753 unsigned int div_stat_fsys2;
754 unsigned char res82[0x4];
755 unsigned int div_stat_peric0;
756 unsigned int div_stat_peric1;
757 unsigned int div_stat_peric2;
758 unsigned int div_stat_peric3;
759 unsigned int div_stat_peric4;
760 unsigned int div_stat_peric5;
761 unsigned char res83[0x10];
762 unsigned int sclk_div_stat_isp;
763 unsigned char res84[0xc];
764 unsigned int div2_stat0;
765 unsigned int div2_stat1;
766 unsigned char res85[0x8];
767 unsigned int div4_stat;
768 unsigned char res86[0x184];
769 unsigned int gate_top_sclk_disp1;
770 unsigned int gate_top_sclk_gen;
771 unsigned char res87[0xc];
772 unsigned int gate_top_sclk_mau;
773 unsigned int gate_top_sclk_fsys;
774 unsigned char res88[0xc];
775 unsigned int gate_top_sclk_peric;
776 unsigned char res89[0x1c];
777 unsigned int gate_top_sclk_isp;
778 unsigned char res90[0xac];
779 unsigned int gate_ip_gscl;
780 unsigned char res91[0x4];
781 unsigned int gate_ip_disp1;
782 unsigned int gate_ip_mfc;
783 unsigned int gate_ip_g3d;
784 unsigned int gate_ip_gen;
785 unsigned char res92[0xc];
786 unsigned int gate_ip_fsys;
787 unsigned char res93[0x8];
788 unsigned int gate_ip_peric;
789 unsigned char res94[0xc];
790 unsigned int gate_ip_peris;
791 unsigned char res95[0x1c];
792 unsigned int gate_block;
793 unsigned char res96[0x1c];
794 unsigned int mcuiop_pwr_ctrl;
795 unsigned char res97[0x5c];
796 unsigned int clkout_cmu_top;
797 unsigned int clkout_cmu_top_div_stat;
798 unsigned char res98[0x37f8];
799 unsigned int src_lex;
800 unsigned char res99[0x1fc];
801 unsigned int mux_stat_lex;
802 unsigned char res100[0xfc];
803 unsigned int div_lex;
804 unsigned char res101[0xfc];
805 unsigned int div_stat_lex;
806 unsigned char res102[0x1fc];
807 unsigned int gate_ip_lex;
808 unsigned char res103[0x1fc];
809 unsigned int clkout_cmu_lex;
810 unsigned int clkout_cmu_lex_div_stat;
811 unsigned char res104[0x3af8];
812 unsigned int div_r0x;
813 unsigned char res105[0xfc];
814 unsigned int div_stat_r0x;
815 unsigned char res106[0x1fc];
816 unsigned int gate_ip_r0x;
817 unsigned char res107[0x1fc];
818 unsigned int clkout_cmu_r0x;
819 unsigned int clkout_cmu_r0x_div_stat;
820 unsigned char res108[0x3af8];
821 unsigned int div_r1x;
822 unsigned char res109[0xfc];
823 unsigned int div_stat_r1x;
824 unsigned char res110[0x1fc];
825 unsigned int gate_ip_r1x;
826 unsigned char res111[0x1fc];
827 unsigned int clkout_cmu_r1x;
828 unsigned int clkout_cmu_r1x_div_stat;
829 unsigned char res112[0x3608];
830 unsigned int bpll_lock;
831 unsigned char res113[0xfc];
832 unsigned int bpll_con0;
833 unsigned int bpll_con1;
834 unsigned char res114[0xe8];
835 unsigned int src_cdrex;
836 unsigned char res115[0x1fc];
837 unsigned int mux_stat_cdrex;
838 unsigned char res116[0xfc];
839 unsigned int div_cdrex;
840 unsigned char res117[0xfc];
841 unsigned int div_stat_cdrex;
842 unsigned char res118[0x2fc];
843 unsigned int gate_ip_cdrex;
844 unsigned char res119[0x10];
845 unsigned int dmc_freq_ctrl;
846 unsigned char res120[0x4];
847 unsigned int drex2_pause;
848 unsigned char res121[0xe0];
849 unsigned int clkout_cmu_cdrex;
850 unsigned int clkout_cmu_cdrex_div_stat;
851 unsigned char res122[0x8];
852 unsigned int lpddr3phy_ctrl;
853 unsigned int lpddr3phy_con0;
854 unsigned int lpddr3phy_con1;
855 unsigned int lpddr3phy_con2;
856 unsigned int lpddr3phy_con3;
857 unsigned int pll_div2_sel;
858 unsigned char res123[0xf5d8];