Lines Matching defs:exynos4x12_clock
240 struct exynos4x12_clock { struct
241 unsigned char res1[0x4200];
242 unsigned int src_leftbus;
243 unsigned char res2[0x1fc];
244 unsigned int mux_stat_leftbus;
245 unsigned char res3[0xfc];
246 unsigned int div_leftbus;
247 unsigned char res4[0xfc];
248 unsigned int div_stat_leftbus;
249 unsigned char res5[0x1fc];
250 unsigned int gate_ip_leftbus;
251 unsigned char res6[0x12c];
252 unsigned int gate_ip_image;
253 unsigned char res7[0xcc];
254 unsigned int clkout_leftbus;
255 unsigned int clkout_leftbus_div_stat;
256 unsigned char res8[0x37f8];
257 unsigned int src_rightbus;
258 unsigned char res9[0x1fc];
259 unsigned int mux_stat_rightbus;
260 unsigned char res10[0xfc];
261 unsigned int div_rightbus;
262 unsigned char res11[0xfc];
263 unsigned int div_stat_rightbus;
264 unsigned char res12[0x1fc];
265 unsigned int gate_ip_rightbus;
266 unsigned char res13[0x15c];
267 unsigned int gate_ip_perir;
268 unsigned char res14[0x9c];
269 unsigned int clkout_rightbus;
270 unsigned int clkout_rightbus_div_stat;
271 unsigned char res15[0x3608];
272 unsigned int epll_lock;
273 unsigned char res16[0xc];
274 unsigned int vpll_lock;
275 unsigned char res17[0xec];
276 unsigned int epll_con0;
277 unsigned int epll_con1;
278 unsigned int epll_con2;
279 unsigned char res18[0x4];
280 unsigned int vpll_con0;
281 unsigned int vpll_con1;
282 unsigned int vpll_con2;
283 unsigned char res19[0xe4];
284 unsigned int src_top0;
285 unsigned int src_top1;
286 unsigned char res20[0x8];
287 unsigned int src_cam;
288 unsigned int src_tv;
289 unsigned int src_mfc;
290 unsigned int src_g3d;
291 unsigned char res21[0x4];
292 unsigned int src_lcd;
293 unsigned int src_isp;
294 unsigned int src_maudio;
295 unsigned int src_fsys;
296 unsigned char res22[0xc];
297 unsigned int src_peril0;
298 unsigned int src_peril1;
299 unsigned int src_cam1;
300 unsigned char res23[0xb4];
301 unsigned int src_mask_top;
302 unsigned char res24[0xc];
303 unsigned int src_mask_cam;
304 unsigned int src_mask_tv;
305 unsigned char res25[0xc];
306 unsigned int src_mask_lcd;
307 unsigned int src_mask_isp;
308 unsigned int src_mask_maudio;
309 unsigned int src_mask_fsys;
310 unsigned char res26[0xc];
311 unsigned int src_mask_peril0;
312 unsigned int src_mask_peril1;
313 unsigned char res27[0xb8];
314 unsigned int mux_stat_top0;
315 unsigned int mux_stat_top1;
316 unsigned char res28[0x10];
317 unsigned int mux_stat_mfc;
318 unsigned int mux_stat_g3d;
319 unsigned char res29[0x28];
320 unsigned int mux_stat_cam1;
321 unsigned char res30[0xb4];
322 unsigned int div_top;
323 unsigned char res31[0xc];
324 unsigned int div_cam;
325 unsigned int div_tv;
326 unsigned int div_mfc;
327 unsigned int div_g3d;
328 unsigned char res32[0x4];
329 unsigned int div_lcd;
330 unsigned int div_isp;
331 unsigned int div_maudio;
332 unsigned int div_fsys0;
333 unsigned int div_fsys1;
334 unsigned int div_fsys2;
335 unsigned int div_fsys3;
336 unsigned int div_peril0;
337 unsigned int div_peril1;
338 unsigned int div_peril2;
339 unsigned int div_peril3;
340 unsigned int div_peril4;
341 unsigned int div_peril5;
342 unsigned int div_cam1;
343 unsigned char res33[0x14];
344 unsigned int div2_ratio;
345 unsigned char res34[0x8c];
346 unsigned int div_stat_top;
347 unsigned char res35[0xc];
348 unsigned int div_stat_cam;
349 unsigned int div_stat_tv;
350 unsigned int div_stat_mfc;
351 unsigned int div_stat_g3d;
352 unsigned char res36[0x4];
353 unsigned int div_stat_lcd;
354 unsigned int div_stat_isp;
355 unsigned int div_stat_maudio;
356 unsigned int div_stat_fsys0;
357 unsigned int div_stat_fsys1;
358 unsigned int div_stat_fsys2;
359 unsigned int div_stat_fsys3;
360 unsigned int div_stat_peril0;
361 unsigned int div_stat_peril1;
362 unsigned int div_stat_peril2;
363 unsigned int div_stat_peril3;
364 unsigned int div_stat_peril4;
365 unsigned int div_stat_peril5;
366 unsigned int div_stat_cam1;
367 unsigned char res37[0x14];
368 unsigned int div2_stat;
369 unsigned char res38[0x29c];
370 unsigned int gate_ip_cam;
371 unsigned int gate_ip_tv;
372 unsigned int gate_ip_mfc;
373 unsigned int gate_ip_g3d;
374 unsigned char res39[0x4];
375 unsigned int gate_ip_lcd;
376 unsigned int gate_ip_isp;
377 unsigned char res40[0x4];
378 unsigned int gate_ip_fsys;
379 unsigned char res41[0x8];
380 unsigned int gate_ip_gps;
381 unsigned int gate_ip_peril;
382 unsigned char res42[0xc];
383 unsigned char res43[0x4];
384 unsigned char res44[0xc];
385 unsigned int gate_block;
386 unsigned char res45[0x8c];
387 unsigned int clkout_cmu_top;
388 unsigned int clkout_cmu_top_div_stat;
389 unsigned char res46[0x3600];
390 unsigned int mpll_lock;
391 unsigned char res47[0xfc];
392 unsigned int mpll_con0;
393 unsigned int mpll_con1;
394 unsigned char res48[0xf0];
395 unsigned int src_dmc;
396 unsigned char res49[0xfc];
397 unsigned int src_mask_dmc;
398 unsigned char res50[0xfc];
399 unsigned int mux_stat_dmc;
400 unsigned char res51[0xfc];
401 unsigned int div_dmc0;
402 unsigned int div_dmc1;
403 unsigned char res52[0xf8];
404 unsigned int div_stat_dmc0;
405 unsigned int div_stat_dmc1;
406 unsigned char res53[0xf8];
407 unsigned int gate_bus_dmc0;
408 unsigned int gate_bus_dmc1;
409 unsigned char res54[0x1f8];
410 unsigned int gate_ip_dmc0;
411 unsigned int gate_ip_dmc1;
412 unsigned char res55[0xf8];
413 unsigned int clkout_cmu_dmc;
414 unsigned int clkout_cmu_dmc_div_stat;
415 unsigned char res56[0x5f8];
416 unsigned int dcgidx_map0;
417 unsigned int dcgidx_map1;
418 unsigned int dcgidx_map2;
419 unsigned char res57[0x14];
420 unsigned int dcgperf_map0;
421 unsigned int dcgperf_map1;
422 unsigned char res58[0x18];
423 unsigned int dvcidx_map;
424 unsigned char res59[0x1c];
425 unsigned int freq_cpu;
426 unsigned int freq_dpm;
427 unsigned char res60[0x18];
428 unsigned int dvsemclk_en;
429 unsigned int maxperf;
430 unsigned char res61[0x8];
431 unsigned int dmc_freq_ctrl;
432 unsigned int dmc_pause_ctrl;
433 unsigned int dddrphy_lock_ctrl;
434 unsigned int c2c_state;
435 unsigned char res62[0x2f60];
436 unsigned int apll_lock;
437 unsigned char res63[0x8];
438 unsigned char res64[0xf4];
439 unsigned int apll_con0;
440 unsigned int apll_con1;
441 unsigned char res65[0xf8];
442 unsigned int src_cpu;
443 unsigned char res66[0x1fc];
444 unsigned int mux_stat_cpu;
445 unsigned char res67[0xfc];
446 unsigned int div_cpu0;
447 unsigned int div_cpu1;
448 unsigned char res68[0xf8];
449 unsigned int div_stat_cpu0;
450 unsigned int div_stat_cpu1;
451 unsigned char res69[0x2f8];
452 unsigned int clk_gate_ip_cpu;
453 unsigned char res70[0xfc];
454 unsigned int clkout_cmu_cpu;
455 unsigned int clkout_cmu_cpu_div_stat;
456 unsigned char res71[0x5f8];
457 unsigned int armclk_stopctrl;
458 unsigned int atclk_stopctrl;
459 unsigned char res72[0x10];
460 unsigned char res73[0x8];
461 unsigned int pwr_ctrl;
462 unsigned int pwr_ctrl2;
463 unsigned char res74[0xd8];
464 unsigned int apll_con0_l8;
465 unsigned int apll_con0_l7;
466 unsigned int apll_con0_l6;
467 unsigned int apll_con0_l5;
468 unsigned int apll_con0_l4;
469 unsigned int apll_con0_l3;
470 unsigned int apll_con0_l2;
471 unsigned int apll_con0_l1;
472 unsigned int iem_control;
473 unsigned char res75[0xdc];
474 unsigned int apll_con1_l8;
475 unsigned int apll_con1_l7;
476 unsigned int apll_con1_l6;
477 unsigned int apll_con1_l5;
478 unsigned int apll_con1_l4;
479 unsigned int apll_con1_l3;
480 unsigned int apll_con1_l2;
481 unsigned int apll_con1_l1;
482 unsigned char res76[0xe0];
483 unsigned int div_iem_l8;
484 unsigned int div_iem_l7;
485 unsigned int div_iem_l6;
486 unsigned int div_iem_l5;
487 unsigned int div_iem_l4;
488 unsigned int div_iem_l3;
489 unsigned int div_iem_l2;
490 unsigned int div_iem_l1;
491 unsigned char res77[0xe0];
492 unsigned int l2_status;
493 unsigned char res78[0xc];
494 unsigned int cpu_status;
495 unsigned char res79[0xc];
496 unsigned int ptm_status;
497 unsigned char res80[0x2edc];
498 unsigned int div_isp0;
499 unsigned int div_isp1;
500 unsigned char res81[0xf8];
501 unsigned int div_stat_isp0;
502 unsigned int div_stat_isp1;
503 unsigned char res82[0x3f8];
504 unsigned int gate_ip_isp0;
505 unsigned int gate_ip_isp1;
506 unsigned char res83[0x1f8];
507 unsigned int clkout_cmu_isp;
508 unsigned int clkout_cmu_ispd_div_stat;
509 unsigned char res84[0xf8];
510 unsigned int cmu_isp_spar0;
511 unsigned int cmu_isp_spar1;
512 unsigned int cmu_isp_spar2;
513 unsigned int cmu_isp_spar3;