Lines Matching refs:phy_con0
142 writel(val, &phy0_ctrl->phy_con0); in ddr3_mem_ctrl_init()
143 writel(val, &phy1_ctrl->phy_con0); in ddr3_mem_ctrl_init()
153 writel(val, &phy0_ctrl->phy_con0); in ddr3_mem_ctrl_init()
154 writel(val, &phy1_ctrl->phy_con0); in ddr3_mem_ctrl_init()
175 writel(val, &phy0_ctrl->phy_con0); in ddr3_mem_ctrl_init()
176 writel(val, &phy1_ctrl->phy_con0); in ddr3_mem_ctrl_init()
492 val = readl(&phy0_ctrl->phy_con0); in ddr3_mem_ctrl_init()
495 writel(val, &phy0_ctrl->phy_con0); in ddr3_mem_ctrl_init()
497 val = readl(&phy1_ctrl->phy_con0); in ddr3_mem_ctrl_init()
500 writel(val, &phy1_ctrl->phy_con0); in ddr3_mem_ctrl_init()
692 writel(PHY_CON0_RESET_VAL, &phy0_ctrl->phy_con0); in ddr3_mem_ctrl_init()
693 writel(PHY_CON0_RESET_VAL, &phy1_ctrl->phy_con0); in ddr3_mem_ctrl_init()
695 setbits_le32(&phy0_ctrl->phy_con0, P0_CMD_EN); in ddr3_mem_ctrl_init()
696 setbits_le32(&phy1_ctrl->phy_con0, P0_CMD_EN); in ddr3_mem_ctrl_init()
734 setbits_le32(&phy0_ctrl->phy_con0, CTRL_SHGATE); in ddr3_mem_ctrl_init()
735 setbits_le32(&phy1_ctrl->phy_con0, CTRL_SHGATE); in ddr3_mem_ctrl_init()