39 	struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;  in ddr3_mem_ctrl_init()  local
44 	phy1_ctrl = (struct exynos5_phy_control *)(samsung_get_base_dmc_phy()  in ddr3_mem_ctrl_init()
57 	writel(val, &phy1_ctrl->phy_con39);  in ddr3_mem_ctrl_init()
63 	writel(val, &phy1_ctrl->phy_con42);  in ddr3_mem_ctrl_init()
66 	if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,  in ddr3_mem_ctrl_init()
67 			  &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17))  in ddr3_mem_ctrl_init()
72 	writel(mem->phy1_pulld_dqs, &phy1_ctrl->phy_con14);  in ddr3_mem_ctrl_init()
82 	writel(mem->phy1_dqs, &phy1_ctrl->phy_con4);  in ddr3_mem_ctrl_init()
85 	writel(mem->phy1_dq, &phy1_ctrl->phy_con6);  in ddr3_mem_ctrl_init()
88 	writel(mem->phy1_tFS, &phy1_ctrl->phy_con10);  in ddr3_mem_ctrl_init()
95 	writel(val, &phy1_ctrl->phy_con12);  in ddr3_mem_ctrl_init()
101 	       &phy1_ctrl->phy_con12);  in ddr3_mem_ctrl_init()
143 		writel(val, &phy1_ctrl->phy_con0);  in ddr3_mem_ctrl_init()
148 		writel(val, &phy1_ctrl->phy_con2);  in ddr3_mem_ctrl_init()
154 		writel(val, &phy1_ctrl->phy_con0);  in ddr3_mem_ctrl_init()
163 		writel(val, &phy1_ctrl->phy_con12);  in ddr3_mem_ctrl_init()
169 		writel(val, &phy1_ctrl->phy_con2);  in ddr3_mem_ctrl_init()
176 		writel(val, &phy1_ctrl->phy_con0);  in ddr3_mem_ctrl_init()
181 		writel(val, &phy1_ctrl->phy_con1);  in ddr3_mem_ctrl_init()
200 		writel(0, &phy1_ctrl->phy_con14);  in ddr3_mem_ctrl_init()
210 		writel(val, &phy1_ctrl->phy_con12);  in ddr3_mem_ctrl_init()
447 	struct exynos5420_phy_control *phy0_ctrl, *phy1_ctrl;  in ddr3_mem_ctrl_init()  local
457 	phy1_ctrl = (struct exynos5420_phy_control *)(samsung_get_base_dmc_phy()  in ddr3_mem_ctrl_init()
497 	val = readl(&phy1_ctrl->phy_con0);  in ddr3_mem_ctrl_init()
500 	writel(val, &phy1_ctrl->phy_con0);  in ddr3_mem_ctrl_init()
506 	writel(val, &phy1_ctrl->phy_con42);  in ddr3_mem_ctrl_init()
513 	val = readl(&phy1_ctrl->phy_con26);  in ddr3_mem_ctrl_init()
516 	writel(val, &phy1_ctrl->phy_con26);  in ddr3_mem_ctrl_init()
527 	writel(val, &phy1_ctrl->phy_con39);  in ddr3_mem_ctrl_init()
530 	if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,  in ddr3_mem_ctrl_init()
531 			  &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17))  in ddr3_mem_ctrl_init()
535 	clrbits_le32(&phy1_ctrl->phy_con16, ZQ_CLK_DIV_EN);  in ddr3_mem_ctrl_init()
541 	val = readl(&phy1_ctrl->phy_con14);  in ddr3_mem_ctrl_init()
543 	writel(val, &phy1_ctrl->phy_con14);  in ddr3_mem_ctrl_init()
651 		lock1_info = readl(&phy1_ctrl->phy_con13);  in ddr3_mem_ctrl_init()
693 		writel(PHY_CON0_RESET_VAL, &phy1_ctrl->phy_con0);  in ddr3_mem_ctrl_init()
696 		setbits_le32(&phy1_ctrl->phy_con0, P0_CMD_EN);  in ddr3_mem_ctrl_init()
701 		writel(val, &phy1_ctrl->phy_con2);  in ddr3_mem_ctrl_init()
707 		val =  readl(&phy1_ctrl->phy_con1);  in ddr3_mem_ctrl_init()
709 		writel(val, &phy1_ctrl->phy_con1);  in ddr3_mem_ctrl_init()
718 		n_lock_r = readl(&phy1_ctrl->phy_con12);  in ddr3_mem_ctrl_init()
721 		writel(n_lock_r, &phy1_ctrl->phy_con12);  in ddr3_mem_ctrl_init()
732 		setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN);  in ddr3_mem_ctrl_init()
735 		setbits_le32(&phy1_ctrl->phy_con0, CTRL_SHGATE);  in ddr3_mem_ctrl_init()
741 		val = readl(&phy1_ctrl->phy_con1);  in ddr3_mem_ctrl_init()
743 		writel(val, &phy1_ctrl->phy_con1);  in ddr3_mem_ctrl_init()
776 		writel(0, &phy1_ctrl->phy_con14);  in ddr3_mem_ctrl_init()
789 		writel((val + n_lock_w_phy1), &phy1_ctrl->phy_con12);  in ddr3_mem_ctrl_init()
792 		setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN);  in ddr3_mem_ctrl_init()
805 		dmc_set_read_offset_value(phy1_ctrl, readl(&pmu->pmu_spare2));  in ddr3_mem_ctrl_init()
809 		software_find_read_offset(phy1_ctrl, 1,  in ddr3_mem_ctrl_init()
813 		writel(dmc_get_read_offset_value(phy1_ctrl), &pmu->pmu_spare2);  in ddr3_mem_ctrl_init()