39 	struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;  in ddr3_mem_ctrl_init()  local
43 	phy0_ctrl = (struct exynos5_phy_control *)samsung_get_base_dmc_phy();  in ddr3_mem_ctrl_init()
56 	writel(val, &phy0_ctrl->phy_con39);  in ddr3_mem_ctrl_init()
62 	writel(val, &phy0_ctrl->phy_con42);  in ddr3_mem_ctrl_init()
66 	if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,  in ddr3_mem_ctrl_init()
67 			  &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17))  in ddr3_mem_ctrl_init()
71 	writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14);  in ddr3_mem_ctrl_init()
81 	writel(mem->phy0_dqs, &phy0_ctrl->phy_con4);  in ddr3_mem_ctrl_init()
84 	writel(mem->phy0_dq, &phy0_ctrl->phy_con6);  in ddr3_mem_ctrl_init()
87 	writel(mem->phy0_tFS, &phy0_ctrl->phy_con10);  in ddr3_mem_ctrl_init()
94 	writel(val, &phy0_ctrl->phy_con12);  in ddr3_mem_ctrl_init()
99 	       &phy0_ctrl->phy_con12);  in ddr3_mem_ctrl_init()
142 		writel(val, &phy0_ctrl->phy_con0);  in ddr3_mem_ctrl_init()
147 		writel(val, &phy0_ctrl->phy_con2);  in ddr3_mem_ctrl_init()
153 		writel(val, &phy0_ctrl->phy_con0);  in ddr3_mem_ctrl_init()
162 		writel(val, &phy0_ctrl->phy_con12);  in ddr3_mem_ctrl_init()
168 		writel(val, &phy0_ctrl->phy_con2);  in ddr3_mem_ctrl_init()
175 		writel(val, &phy0_ctrl->phy_con0);  in ddr3_mem_ctrl_init()
180 		writel(val, &phy0_ctrl->phy_con1);  in ddr3_mem_ctrl_init()
199 		writel(0, &phy0_ctrl->phy_con14);  in ddr3_mem_ctrl_init()
209 		writel(val, &phy0_ctrl->phy_con12);  in ddr3_mem_ctrl_init()
447 	struct exynos5420_phy_control *phy0_ctrl, *phy1_ctrl;  in ddr3_mem_ctrl_init()  local
456 	phy0_ctrl = (struct exynos5420_phy_control *)samsung_get_base_dmc_phy();  in ddr3_mem_ctrl_init()
492 	val = readl(&phy0_ctrl->phy_con0);  in ddr3_mem_ctrl_init()
495 	writel(val, &phy0_ctrl->phy_con0);  in ddr3_mem_ctrl_init()
505 	writel(val, &phy0_ctrl->phy_con42);  in ddr3_mem_ctrl_init()
508 	val = readl(&phy0_ctrl->phy_con26);  in ddr3_mem_ctrl_init()
511 	writel(val, &phy0_ctrl->phy_con26);  in ddr3_mem_ctrl_init()
526 	writel(val, &phy0_ctrl->phy_con39);  in ddr3_mem_ctrl_init()
530 	if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,  in ddr3_mem_ctrl_init()
531 			  &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17))  in ddr3_mem_ctrl_init()
534 	clrbits_le32(&phy0_ctrl->phy_con16, ZQ_CLK_DIV_EN);  in ddr3_mem_ctrl_init()
538 	val = readl(&phy0_ctrl->phy_con14);  in ddr3_mem_ctrl_init()
540 	writel(val, &phy0_ctrl->phy_con14);  in ddr3_mem_ctrl_init()
641 		lock0_info = readl(&phy0_ctrl->phy_con13);  in ddr3_mem_ctrl_init()
692 		writel(PHY_CON0_RESET_VAL, &phy0_ctrl->phy_con0);  in ddr3_mem_ctrl_init()
695 		setbits_le32(&phy0_ctrl->phy_con0, P0_CMD_EN);  in ddr3_mem_ctrl_init()
700 		writel(val, &phy0_ctrl->phy_con2);  in ddr3_mem_ctrl_init()
703 		val =  readl(&phy0_ctrl->phy_con1);  in ddr3_mem_ctrl_init()
705 		writel(val, &phy0_ctrl->phy_con1);  in ddr3_mem_ctrl_init()
712 		n_lock_r = readl(&phy0_ctrl->phy_con12);  in ddr3_mem_ctrl_init()
715 		writel(n_lock_r, &phy0_ctrl->phy_con12);  in ddr3_mem_ctrl_init()
731 		setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN);  in ddr3_mem_ctrl_init()
734 		setbits_le32(&phy0_ctrl->phy_con0, CTRL_SHGATE);  in ddr3_mem_ctrl_init()
737 		val = readl(&phy0_ctrl->phy_con1);  in ddr3_mem_ctrl_init()
739 		writel(val, &phy0_ctrl->phy_con1);  in ddr3_mem_ctrl_init()
775 		writel(0, &phy0_ctrl->phy_con14);  in ddr3_mem_ctrl_init()
788 		writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12);  in ddr3_mem_ctrl_init()
791 		setbits_le32(&phy0_ctrl->phy_con2, DLL_DESKEW_EN);  in ddr3_mem_ctrl_init()
804 		dmc_set_read_offset_value(phy0_ctrl, readl(&pmu->pmu_spare1));  in ddr3_mem_ctrl_init()
807 		software_find_read_offset(phy0_ctrl, 0,  in ddr3_mem_ctrl_init()
812 		writel(dmc_get_read_offset_value(phy0_ctrl), &pmu->pmu_spare1);  in ddr3_mem_ctrl_init()