Lines Matching refs:i
346 int i; in get_clk_bit_info() local
354 for (i = 0; info[i].id != PERIPH_ID_NONE; i++) { in get_clk_bit_info()
355 if (info[i].id == peripheral) in get_clk_bit_info()
359 if (info[i].id == PERIPH_ID_NONE) in get_clk_bit_info()
362 return &info[i]; in get_clk_bit_info()
1270 unsigned int i; in exynos5_set_epll_clk() local
1283 for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) { in exynos5_set_epll_clk()
1284 if (exynos5_epll_div[i].freq_out == rate) in exynos5_set_epll_clk()
1288 if (i == ARRAY_SIZE(exynos5_epll_div)) in exynos5_set_epll_clk()
1291 epll_con_k = exynos5_epll_div[i].k_dsm << 0; in exynos5_set_epll_clk()
1292 epll_con |= exynos5_epll_div[i].en_lock_det << in exynos5_set_epll_clk()
1294 epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT; in exynos5_set_epll_clk()
1295 epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT; in exynos5_set_epll_clk()
1296 epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT; in exynos5_set_epll_clk()
1303 lockcnt = 3000 * exynos5_epll_div[i].p_div; in exynos5_set_epll_clk()
1399 int i; in clock_calc_best_scalar() local
1419 for (i = 1; i <= loops; i++) { in clock_calc_best_scalar()
1421 max(min(input_rate / i / target_rate, cap), 1U); in clock_calc_best_scalar()
1422 const unsigned int effective_rate = input_rate / i / in clock_calc_best_scalar()
1426 debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div, in clock_calc_best_scalar()
1431 best_main_scalar = i; in clock_calc_best_scalar()