108 	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN);  in dm365_pll2_init()
115 	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9);  in dm365_pll2_init()
116 	setbits_le32(&dv_pll1_regs->pllctl,  in dm365_pll2_init()
123 	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC);  in dm365_pll2_init()
126 	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);  in dm365_pll2_init()
131 	setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);  in dm365_pll2_init()
136 	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);  in dm365_pll2_init()
139 	writel(pllm, &dv_pll1_regs->pllm);  in dm365_pll2_init()
140 	writel(prediv, &dv_pll1_regs->prediv);  in dm365_pll2_init()
142 	writel(PLL_POSTDEN, &dv_pll1_regs->postdiv);  in dm365_pll2_init()
146 		PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);  in dm365_pll2_init()
149 		&dv_pll1_regs->secctl);  in dm365_pll2_init()
151 	writel(PLLSECCTL_STOPMODE, &dv_pll1_regs->secctl);  in dm365_pll2_init()
153 	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);  in dm365_pll2_init()
156 	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV1, &dv_pll1_regs->plldiv1);  in dm365_pll2_init()
157 	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV2, &dv_pll1_regs->plldiv2);  in dm365_pll2_init()
158 	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV3, &dv_pll1_regs->plldiv3);  in dm365_pll2_init()
159 	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV4, &dv_pll1_regs->plldiv4);  in dm365_pll2_init()
160 	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV5, &dv_pll1_regs->plldiv5);  in dm365_pll2_init()
163 	writel(PLLCMD_GOSET, &dv_pll1_regs->pllcmd);  in dm365_pll2_init()
175 	setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);  in dm365_pll2_init()