31 	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN);  in dm365_pll1_init()
33 	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);  in dm365_pll1_init()
34 	setbits_le32(&dv_pll0_regs->pllctl,  in dm365_pll1_init()
41 	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC);  in dm365_pll1_init()
44 	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);  in dm365_pll1_init()
49 	setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);  in dm365_pll1_init()
54 	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);  in dm365_pll1_init()
57 	writel(pllmult, &dv_pll0_regs->pllm);  in dm365_pll1_init()
58 	writel(prediv, &dv_pll0_regs->prediv);  in dm365_pll1_init()
62 		PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);  in dm365_pll1_init()
65 		&dv_pll0_regs->secctl);  in dm365_pll1_init()
67 	writel(PLLSECCTL_STOPMODE, &dv_pll0_regs->secctl);  in dm365_pll1_init()
69 	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);  in dm365_pll1_init()
72 	writel(PLL_POSTDEN, &dv_pll0_regs->postdiv);  in dm365_pll1_init()
75 	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1);  in dm365_pll1_init()
76 	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV2, &dv_pll0_regs->plldiv2);  in dm365_pll1_init()
77 	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV3, &dv_pll0_regs->plldiv3);  in dm365_pll1_init()
78 	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV4, &dv_pll0_regs->plldiv4);  in dm365_pll1_init()
79 	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV5, &dv_pll0_regs->plldiv5);  in dm365_pll1_init()
80 	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV6, &dv_pll0_regs->plldiv6);  in dm365_pll1_init()
81 	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV7, &dv_pll0_regs->plldiv7);  in dm365_pll1_init()
82 	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV8, &dv_pll0_regs->plldiv8);  in dm365_pll1_init()
83 	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV9, &dv_pll0_regs->plldiv9);  in dm365_pll1_init()
88 	writel(PLLCMD_GOSET, &dv_pll0_regs->pllcmd); /* Go */  in dm365_pll1_init()
98 	setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);  in dm365_pll1_init()
270 	if (readl(&dv_pll0_regs->rstype) &  in dm365_por_reset()