Lines Matching defs:dc_disp_reg
176 struct dc_disp_reg { struct
178 uint disp_signal_opt0; /* _DISP_DISP_SIGNAL_OPTIONS0_0 */
179 uint disp_signal_opt1; /* _DISP_DISP_SIGNAL_OPTIONS1_0 */
180 uint disp_win_opt; /* _DISP_DISP_WIN_OPTIONS_0 */
181 uint mem_high_pri; /* _DISP_MEM_HIGH_PRIORITY_0 */
182 uint mem_high_pri_timer; /* _DISP_MEM_HIGH_PRIORITY_TIMER_0 */
183 uint disp_timing_opt; /* _DISP_DISP_TIMING_OPTIONS_0 */
184 uint ref_to_sync; /* _DISP_REF_TO_SYNC_0 */
185 uint sync_width; /* _DISP_SYNC_WIDTH_0 */
186 uint back_porch; /* _DISP_BACK_PORCH_0 */
187 uint disp_active; /* _DISP_DISP_ACTIVE_0 */
188 uint front_porch; /* _DISP_FRONT_PORCH_0 */
191 struct _disp_h_pulse h_pulse[H_PULSE_COUNT];
194 struct _disp_v_pulse0 v_pulse0; /* _DISP_V_PULSE0_ */
195 struct _disp_v_pulse0 v_pulse1; /* _DISP_V_PULSE1_ */
198 struct _disp_v_pulse2 v_pulse3; /* _DISP_V_PULSE2_ */
199 struct _disp_v_pulse2 v_pulse4; /* _DISP_V_PULSE3_ */
202 uint m0_ctrl; /* _DISP_M0_CONTROL_0 */
203 uint m1_ctrl; /* _DISP_M1_CONTROL_0 */
204 uint di_ctrl; /* _DISP_DI_CONTROL_0 */
205 uint pp_ctrl; /* _DISP_PP_CONTROL_0 */
208 uint pp_select[PP_SELECT_COUNT];
211 uint disp_clk_ctrl; /* _DISP_DISP_CLOCK_CONTROL_0 */
212 uint disp_interface_ctrl; /* _DISP_DISP_INTERFACE_CONTROL_0 */
213 uint disp_color_ctrl; /* _DISP_DISP_COLOR_CONTROL_0 */
214 uint shift_clk_opt; /* _DISP_SHIFT_CLOCK_OPTIONS_0 */
215 uint data_enable_opt; /* _DISP_DATA_ENABLE_OPTIONS_0 */
216 uint serial_interface_opt; /* _DISP_SERIAL_INTERFACE_OPTIONS_0 */
217 uint lcd_spi_opt; /* _DISP_LCD_SPI_OPTIONS_0 */
218 uint border_color; /* _DISP_BORDER_COLOR_0 */
221 uint color_key0_lower; /* _DISP_COLOR_KEY0_LOWER_0 */
222 uint color_key0_upper; /* _DISP_COLOR_KEY0_UPPER_0 */
223 uint color_key1_lower; /* _DISP_COLOR_KEY1_LOWER_0 */
224 uint color_key1_upper; /* _DISP_COLOR_KEY1_UPPER_0 */
226 uint reserved0[2]; /* reserved_0[2] */
229 uint cursor_foreground; /* _DISP_CURSOR_FOREGROUND_0 */
230 uint cursor_background; /* _DISP_CURSOR_BACKGROUND_0 */
231 uint cursor_start_addr; /* _DISP_CURSOR_START_ADDR_0 */
232 uint cursor_start_addr_ns; /* _DISP_CURSOR_START_ADDR_NS_0 */
233 uint cursor_pos; /* _DISP_CURSOR_POSITION_0 */
234 uint cursor_pos_ns; /* _DISP_CURSOR_POSITION_NS_0 */
235 uint seq_ctrl; /* _DISP_INIT_SEQ_CONTROL_0 */
238 uint spi_init_seq_data_a; /* _DISP_SPI_INIT_SEQ_DATA_A_0 */
239 uint spi_init_seq_data_b; /* _DISP_SPI_INIT_SEQ_DATA_B_0 */
240 uint spi_init_seq_data_c; /* _DISP_SPI_INIT_SEQ_DATA_C_0 */
241 uint spi_init_seq_data_d; /* _DISP_SPI_INIT_SEQ_DATA_D_0 */
243 uint reserved1[0x39]; /* reserved1[0x39], */
246 uint dc_mccif_fifoctrl; /* _DISP_DC_MCCIF_FIFOCTRL_0 */
247 uint mccif_disp0a_hyst; /* _DISP_MCCIF_DISPLAY0A_HYST_0 */
248 uint mccif_disp0b_hyst; /* _DISP_MCCIF_DISPLAY0B_HYST_0 */
249 uint mccif_disp0c_hyst; /* _DISP_MCCIF_DISPLAY0C_HYST_0 */
250 uint mccif_disp1b_hyst; /* _DISP_MCCIF_DISPLAY1B_HYST_0 */
252 uint reserved2[0x3b]; /* reserved2[0x3b] */
255 uint dac_crt_ctrl; /* _DISP_DAC_CRT_CTRL_0 */
256 uint disp_misc_ctrl; /* _DISP_DISP_MISC_CONTROL_0 */
258 u32 rsvd_4c2[34]; /* 4c2 - 4e3 */
261 u32 blend_background_color; /* _DISP_BLEND_BACKGROUND_COLOR_0 */