Lines Matching defs:dc_com_reg
82 struct dc_com_reg { struct
84 uint crc_ctrl; /* _COM_CRC_CONTROL_0 */
85 uint crc_checksum; /* _COM_CRC_CHECKSUM_0 */
88 uint pin_output_enb[PIN_REG_COUNT];
91 uint pin_output_polarity[PIN_REG_COUNT];
94 uint pin_output_data[PIN_REG_COUNT];
97 uint pin_input_enb[PIN_REG_COUNT];
100 uint pin_input_data0; /* _COM_PIN_INPUT_DATA0_0 */
101 uint pin_input_data1; /* _COM_PIN_INPUT_DATA1_0 */
104 uint pin_output_sel[PIN_OUTPUT_SEL_COUNT];
107 uint pin_misc_ctrl; /* _COM_PIN_MISC_CONTROL_0 */
108 uint pm0_ctrl; /* _COM_PM0_CONTROL_0 */
109 uint pm0_duty_cycle; /* _COM_PM0_DUTY_CYCLE_0 */
110 uint pm1_ctrl; /* _COM_PM1_CONTROL_0 */
111 uint pm1_duty_cycle; /* _COM_PM1_DUTY_CYCLE_0 */
112 uint spi_ctrl; /* _COM_SPI_CONTROL_0 */
113 uint spi_start_byte; /* _COM_SPI_START_BYTE_0 */
114 uint hspi_wr_data_ab; /* _COM_HSPI_WRITE_DATA_AB_0 */
115 uint hspi_wr_data_cd; /* _COM_HSPI_WRITE_DATA_CD */
116 uint hspi_cs_dc; /* _COM_HSPI_CS_DC_0 */
117 uint scratch_reg_a; /* _COM_SCRATCH_REGISTER_A_0 */
118 uint scratch_reg_b; /* _COM_SCRATCH_REGISTER_B_0 */
119 uint gpio_ctrl; /* _COM_GPIO_CTRL_0 */
120 uint gpio_debounce_cnt; /* _COM_GPIO_DEBOUNCE_COUNTER_0 */
121 uint crc_checksum_latched; /* _COM_CRC_CHECKSUM_LATCHED_0 */