asm/arch-tegra/clock.h

4  * SPDX-License-Identifier:	GPL-2.0+
30  * register. As such, the U-Boot clock driver is currently a bit lazy, and
40 #include <asm/arch/clock-tables.h>
53  * @param id	clock id
62 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
68  * @param clkid	clock id
69  * @param pllout	pll output id
72  * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
78  * Read low-level parameters of a PLL.
80  * @param id	clock id to read (note: USB is not supported)
87  * @returns 0 if ok, -1 on error (invalid clock id)
95  * @param id	clock id
102  * @param id	clock id
109  * @param id		clock id
144  * @param cpu		cpu number (0 or 1 on Tegra2, 0-3 on Tegra3)
146  * @param reset		1 to assert reset, 0 to de-assert
155  * Warning: This function is only for use pre-relocation. Please use
169  * @param source	source clock (0-15 depending on mux_bits)
179  * Warning: This function is only for use pre-relocation. Please use
190  * Returns the current parent clock ID of a given peripheral. This can be
192  * specific knowledge of system-level clock tree structure.
195  * @return clock ID of the peripheral's current parent clock
204  * @param parent	PLL id of required parent clock
206  * @return rate selected in Hz, or -1U if something went wrong
217  * @param parent	PLL id of parent clock (used to calculate rate, you
231  * @param parent	PLL id of required parent clock
233  * @param extra_div	value for the second-stage divisor (NULL if one is
235  * @return rate selected in Hz, or -1U if something went wrong
243  * @param parent	PLL id of clock to check
249  * Start up a UART using low-level calls
252  * function provides a way to set up a UART using low-level calls which
255  * @param periph_id	Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1)
260  * Decode a peripheral ID from a device tree node.
263  * the second cell, which is the clock number / peripheral ID.
267  * @return peripheral ID, or PERIPH_ID_NONE if none
281  * @return 0 if ok, -1 on error
301  * Given a peripheral ID, determine where the mux bits are in the peripheral
302  * clock's register, the number of divider bits the clock has, and the SoC-
305  * This is an internal API between the core Tegra clock code and the SoC-
311  * @param type          Set to the SoC-specific clock type
312  * @return 0 on success, -1 on error
318  * Given a peripheral ID and clock source mux value, determine the clock_id
321  * This is an internal API between the core Tegra clock code and the SoC-
331  * Given a peripheral ID and the required source clock, this returns which
337  * @param source        PLL id of required parent clock
340  * @return mux value (0-4, or -1 if not found)
346  * Convert a device tree clock ID to our peripheral ID. They are mostly
347  * the same but we are very cautious so we check that a valid clock ID is
350  * @param clk_id        Clock ID according to tegra30 device tree binding
351  * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
369  * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
374 /* return 1 if a peripheral ID is in range */
375 #define clock_type_id_isvalid(id) ((id) >= 0 && \  argument
376 		(id) < CLOCK_TYPE_COUNT)
379 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \  argument
380 		(id) < PERIPHC_COUNT)
382 /* SoC-specific TSC init */
387 /* Number of PLL-based clocks (i.e. not OSC, MCLK or 32KHz) */
388 #define CLOCK_ID_PLL_COUNT	(CLOCK_ID_COUNT - 3)
417  * @param clk_id	Clock ID to output (1, 2 or 3)
418  * @return 0 if OK. -ve on error