asm/arch-mx7ulp/scg.h

256 typedef struct scg_regs {  struct
257 	u32 verid;	/* VERSION_ID */
258 	u32 param;	/*  PARAMETER */
259 	u32 rsvd11[2];
261 	u32 csr;	/*  Clock Status Register */
262 	u32 rccr;	/*  Run Clock Control Register */
263 	u32 vccr;	/*  VLPR Clock Control Register */
264 	u32 hccr;	/*  HSRUN Clock Control Register */
265 	u32 clkoutcnfg;	/*  SCG CLKOUT Configuration Register */
266 	u32 rsvd12[3];
267 	u32 ddrccr;	/*  SCG DDR Clock Control Register */
268 	u32 rsvd13[3];
269 	u32 nicccr;	/*  NIC Clock Control Register */
270 	u32 niccsr;	/*  NIC Clock Status Register */
271 	u32 rsvd10[46];
273 	u32 sosccsr;	/*  System OSC Control Status Register, offset 0x100 */
274 	u32 soscdiv;	/*  System OSC Divide Register */
275 	u32 sosccfg;	/*  System Oscillator Configuration Register */
276 	u32 sosctest;	/*  System Oscillator Test Register */
277 	u32 rsvd20[60];
279 	u32 sirccsr;	/*  Slow IRC Control Status Register, offset 0x200 */
280 	u32 sircdiv;	/*  Slow IRC Divide Register */
281 	u32 sirccfg;	/*  Slow IRC Configuration Register */
282 	u32 sirctrim;	/*  Slow IRC Trim Register */
283 	u32 loptrim;	/*  Low Power Oscillator Trim Register */
284 	u32 sirctest;	/*  Slow IRC Test Register */
285 	u32 rsvd30[58];
287 	u32 firccsr;	/*  Fast IRC Control Status Register, offset 0x300 */
288 	u32 fircdiv;
289 	u32 firccfg;
290 	u32 firctcfg;	/*  Fast IRC Trim Configuration Register */
291 	u32 firctriml;	/*  Fast IRC Trim Low Register */
292 	u32 firctrimh;
293 	u32 fircstat;	/*  Fast IRC Status Register */
294 	u32 firctest;	/*  Fast IRC Test Register */
295 	u32 rsvd40[56];
297 	u32 rtccsr;	/*  RTC OSC Control Status Register, offset 0x400 */
298 	u32 rsvd50[63];
300 	u32 apllcsr; /*  Auxiliary PLL Control Status Register, offset 0x500 */
301 	u32 aplldiv;	/*  Auxiliary PLL Divider Register */
302 	u32 apllcfg;	/*  Auxiliary PLL Configuration Register */
303 	u32 apllpfd;	/*  Auxiliary PLL PFD Register */
304 	u32 apllnum;	/*  Auxiliary PLL Numerator Register */
305 	u32 aplldenom;	/*  Auxiliary PLL Denominator Register */
306 	u32 apllss;	/*  Auxiliary PLL Spread Spectrum Register */
307 	u32 rsvd60[55];
308 	u32 apllock_cnfg; /*  Auxiliary PLL LOCK Configuration Register */
309 	u32 rsvd61[1];
311 	u32 spllcsr;	/*  System PLL Control Status Register, offset 0x600 */
312 	u32 splldiv;	/*  System PLL Divide Register */
313 	u32 spllcfg;	/*  System PLL Configuration Register */
314 	u32 spllpfd;	/*  System PLL Test Register */
315 	u32 spllnum;	/*  System PLL Numerator Register */
316 	u32 splldenom;	/*  System PLL Denominator Register */
317 	u32 spllss;	/*  System PLL Spread Spectrum Register */
318 	u32 rsvd70[55];
319 	u32 spllock_cnfg;	/*  System PLL LOCK Configuration Register */
320 	u32 rsvd71[1];
322 	u32 upllcsr;	/*  USB PLL Control Status Register, offset 0x700 */
323 	u32 uplldiv;	/*  USB PLL Divide Register */
324 	u32 upllcfg;	/*  USB PLL Configuration Register */