Lines Matching defs:ccsr_gur
178 struct ccsr_gur { struct
179 u32 porsr1; /* POR status 1 */
180 u32 porsr2; /* POR status 2 */
181 u8 res_008[0x20-0x8];
182 u32 gpporcr1; /* General-purpose POR configuration */
183 u32 gpporcr2; /* General-purpose POR configuration 2 */
184 u32 gpporcr3;
185 u32 gpporcr4;
186 u8 res_030[0x60-0x30];
191 u32 dcfg_fusesr; /* Fuse status register */
192 u8 res_064[0x70-0x64];
193 u32 devdisr; /* Device disable control 1 */
194 u32 devdisr2; /* Device disable control 2 */
195 u32 devdisr3; /* Device disable control 3 */
196 u32 devdisr4; /* Device disable control 4 */
197 u32 devdisr5; /* Device disable control 5 */
198 u32 devdisr6; /* Device disable control 6 */
199 u8 res_088[0x94-0x88];
200 u32 coredisr; /* Device disable control 7 */
225 u8 res_098[0xa0-0x98];
226 u32 pvr; /* Processor version */
227 u32 svr; /* System version */
228 u8 res_0a8[0x100-0xa8];
229 u32 rcwsr[30]; /* Reset control word status */
253 u8 res_178[0x200-0x178];
254 u32 scratchrw[16]; /* Scratch Read/Write */
255 u8 res_240[0x300-0x240];
256 u32 scratchw1r[4]; /* Scratch Read (Write once) */
257 u8 res_310[0x400-0x310];
258 u32 bootlocptrl; /* Boot location pointer low-order addr */
259 u32 bootlocptrh; /* Boot location pointer high-order addr */
260 u8 res_408[0x520-0x408];
261 u32 usb1_amqr;
262 u32 usb2_amqr;
263 u8 res_528[0x530-0x528]; /* add more registers when needed */
264 u32 sdmm1_amqr;
265 u8 res_534[0x550-0x534]; /* add more registers when needed */
266 u32 sata1_amqr;
267 u32 sata2_amqr;
268 u8 res_558[0x570-0x558]; /* add more registers when needed */
269 u32 misc1_amqr;
270 u8 res_574[0x590-0x574]; /* add more registers when needed */
271 u32 spare1_amqr;
272 u32 spare2_amqr;
273 u8 res_598[0x620-0x598]; /* add more registers when needed */
274 u32 gencr[7]; /* General Control Registers */
275 u8 res_63c[0x640-0x63c]; /* add more registers when needed */
276 u32 cgensr1; /* Core General Status Register */
277 u8 res_644[0x660-0x644]; /* add more registers when needed */
278 u32 cgencr1; /* Core General Control Register */
279 u8 res_664[0x740-0x664]; /* add more registers when needed */
280 u32 tp_ityp[64]; /* Topology Initiator Type Register */
281 struct {
284 } tp_cluster[4]; /* Core cluster n Topology Register */
285 u8 res_864[0x920-0x864]; /* add more registers when needed */
286 u32 ioqoscr[8]; /*I/O Quality of Services Register */
287 u32 uccr;
288 u8 res_944[0x960-0x944]; /* add more registers when needed */
289 u32 ftmcr;
290 u8 res_964[0x990-0x964]; /* add more registers when needed */
291 u32 coredisablesr;
292 u8 res_994[0xa00-0x994]; /* add more registers when needed */
293 u32 sdbgcr; /*Secure Debug Confifuration Register */
294 u8 res_a04[0xbf8-0xa04]; /* add more registers when needed */
295 u32 ipbrr1;
296 u32 ipbrr2;
297 u8 res_858[0x1000-0xc00];