arm/dts/r8a7796.dtsi

11 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
158 			clocks = <&cpg CPG_MOD 408>;
161 			resets = <&cpg 408>;
180 			clocks = <&cpg CPG_MOD 402>;
182 			resets = <&cpg 402>;
196 			clocks = <&cpg CPG_MOD 912>;
198 			resets = <&cpg 912>;
211 			clocks = <&cpg CPG_MOD 911>;
213 			resets = <&cpg 911>;
226 			clocks = <&cpg CPG_MOD 910>;
228 			resets = <&cpg 910>;
241 			clocks = <&cpg CPG_MOD 909>;
243 			resets = <&cpg 909>;
256 			clocks = <&cpg CPG_MOD 908>;
258 			resets = <&cpg 908>;
271 			clocks = <&cpg CPG_MOD 907>;
273 			resets = <&cpg 907>;
286 			clocks = <&cpg CPG_MOD 906>;
288 			resets = <&cpg 906>;
301 			clocks = <&cpg CPG_MOD 905>;
303 			resets = <&cpg 905>;
331 		cpg: clock-controller@e6150000 {  label
332 			compatible = "renesas,r8a7796-cpg-mssr";
366 			clocks = <&cpg CPG_MOD 926>;
368 			resets = <&cpg 926>;
379 			clocks = <&cpg CPG_MOD 931>;
381 			resets = <&cpg 931>;
396 			clocks = <&cpg CPG_MOD 930>;
398 			resets = <&cpg 930>;
413 			clocks = <&cpg CPG_MOD 929>;
415 			resets = <&cpg 929>;
430 			clocks = <&cpg CPG_MOD 928>;
432 			resets = <&cpg 928>;
446 			clocks = <&cpg CPG_MOD 927>;
448 			resets = <&cpg 927>;
462 			clocks = <&cpg CPG_MOD 919>;
464 			resets = <&cpg 919>;
478 			clocks = <&cpg CPG_MOD 918>;
480 			resets = <&cpg 918>;
492 			clocks = <&cpg CPG_MOD 916>,
493 			       <&cpg CPG_CORE R8A7796_CLK_CANFD>,
496 			assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
499 			resets = <&cpg 916>;
508 			clocks = <&cpg CPG_MOD 915>,
509 			       <&cpg CPG_CORE R8A7796_CLK_CANFD>,
512 			assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
515 			resets = <&cpg 915>;
525 			clocks = <&cpg CPG_MOD 914>,
526 			       <&cpg CPG_CORE R8A7796_CLK_CANFD>,
529 			assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
532 			resets = <&cpg 914>;
580 			clocks = <&cpg CPG_MOD 812>;
582 			resets = <&cpg 812>;
595 			clocks = <&cpg CPG_MOD 520>,
596 				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
603 			resets = <&cpg 520>;
613 			clocks = <&cpg CPG_MOD 519>,
614 				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
621 			resets = <&cpg 519>;
631 			clocks = <&cpg CPG_MOD 518>,
632 				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
639 			resets = <&cpg 518>;
649 			clocks = <&cpg CPG_MOD 517>,
650 				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
656 			resets = <&cpg 517>;
666 			clocks = <&cpg CPG_MOD 516>,
667 				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
673 			resets = <&cpg 516>;
682 			clocks = <&cpg CPG_MOD 207>,
683 				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
690 			resets = <&cpg 207>;
699 			clocks = <&cpg CPG_MOD 206>,
700 				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
707 			resets = <&cpg 206>;
716 			clocks = <&cpg CPG_MOD 310>,
717 				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
721 			resets = <&cpg 310>;
730 			clocks = <&cpg CPG_MOD 204>,
731 				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
737 			resets = <&cpg 204>;
746 			clocks = <&cpg CPG_MOD 203>,
747 				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
753 			resets = <&cpg 203>;
762 			clocks = <&cpg CPG_MOD 202>,
763 				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
770 			resets = <&cpg 202>;
779 			clocks = <&cpg CPG_MOD 211>;
784 			resets = <&cpg 211>;
795 			clocks = <&cpg CPG_MOD 210>;
800 			resets = <&cpg 210>;
811 			clocks = <&cpg CPG_MOD 209>;
815 			resets = <&cpg 209>;
826 			clocks = <&cpg CPG_MOD 208>;
830 			resets = <&cpg 208>;
862 			clocks = <&cpg CPG_MOD 219>;
865 			resets = <&cpg 219>;
896 			clocks = <&cpg CPG_MOD 218>;
899 			resets = <&cpg 218>;
930 			clocks = <&cpg CPG_MOD 217>;
933 			resets = <&cpg 217>;
942 			clocks = <&cpg CPG_MOD 314>;
945 			resets = <&cpg 314>;
953 			clocks = <&cpg CPG_MOD 313>;
956 			resets = <&cpg 313>;
964 			clocks = <&cpg CPG_MOD 312>;
967 			resets = <&cpg 312>;
975 			clocks = <&cpg CPG_MOD 311>;
978 			resets = <&cpg 311>;
990 			clocks = <&cpg CPG_MOD 522>;
992 			resets = <&cpg 522>;