57 	u32 tmp;  in set_r5_halt_mode()  local
59 	tmp = readl(&rpu_base->rpu0_cfg);  in set_r5_halt_mode()
61 		tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;  in set_r5_halt_mode()
63 		tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK;  in set_r5_halt_mode()
64 	writel(tmp, &rpu_base->rpu0_cfg);  in set_r5_halt_mode()
67 		tmp = readl(&rpu_base->rpu1_cfg);  in set_r5_halt_mode()
69 			tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;  in set_r5_halt_mode()
71 			tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK;  in set_r5_halt_mode()
72 		writel(tmp, &rpu_base->rpu1_cfg);  in set_r5_halt_mode()
78 	u32 tmp;  in set_r5_tcm_mode()  local
80 	tmp = readl(&rpu_base->rpu_glbl_ctrl);  in set_r5_tcm_mode()
82 		tmp &= ~ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;  in set_r5_tcm_mode()
83 		tmp |= ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK |  in set_r5_tcm_mode()
86 		tmp |= ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;  in set_r5_tcm_mode()
87 		tmp &= ~(ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK |  in set_r5_tcm_mode()
91 	writel(tmp, &rpu_base->rpu_glbl_ctrl);  in set_r5_tcm_mode()
96 	u32 tmp;  in set_r5_reset()  local
98 	tmp = readl(&crlapb_base->rst_lpd_top);  in set_r5_reset()
99 	tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |  in set_r5_reset()
103 		tmp |= ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK;  in set_r5_reset()
105 	writel(tmp, &crlapb_base->rst_lpd_top);  in set_r5_reset()
110 	u32 tmp;  in release_r5_reset()  local
112 	tmp = readl(&crlapb_base->rst_lpd_top);  in release_r5_reset()
113 	tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |  in release_r5_reset()
117 		tmp &= ~ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK;  in release_r5_reset()
119 	writel(tmp, &crlapb_base->rst_lpd_top);  in release_r5_reset()
124 	u32 tmp;  in enable_clock_r5()  local
126 	tmp = readl(&crlapb_base->cpu_r5_ctrl);  in enable_clock_r5()
127 	tmp |= ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK;  in enable_clock_r5()
128 	writel(tmp, &crlapb_base->cpu_r5_ctrl);  in enable_clock_r5()
169 	u32 tmp;  in set_r5_start()  local
171 	tmp = readl(&rpu_base->rpu0_cfg);  in set_r5_start()
173 		tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK;  in set_r5_start()
175 		tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK;  in set_r5_start()
176 	writel(tmp, &rpu_base->rpu0_cfg);  in set_r5_start()
178 	tmp = readl(&rpu_base->rpu1_cfg);  in set_r5_start()
180 		tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK;  in set_r5_start()
182 		tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK;  in set_r5_start()
183 	writel(tmp, &rpu_base->rpu1_cfg);  in set_r5_start()