44 	int i;  in serdes_get_first_lane()  local
68 	for (i = 0; i < SRDS_MAX_LANES; i++) {  in serdes_get_first_lane()
69 		if (serdes_get_prtcl(sd, cfg, i) == device)  in serdes_get_first_lane()
70 			return i;  in serdes_get_first_lane()
154 	int i;  in setup_serdes_volt()  local
180 	for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {  in setup_serdes_volt()
181 		reg = in_be32(&serdes1_base->lane[i].gcr0);  in setup_serdes_volt()
183 		out_be32(&serdes1_base->lane[i].gcr0, reg);  in setup_serdes_volt()
190 	for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {  in setup_serdes_volt()
191 		reg = in_be32(&serdes2_base->lane[i].gcr0);  in setup_serdes_volt()
193 		out_be32(&serdes2_base->lane[i].gcr0, reg);  in setup_serdes_volt()
200 	for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {  in setup_serdes_volt()
201 		reg = in_be32(&serdes1_base->bank[i].rstctl);  in setup_serdes_volt()
204 		out_be32(&serdes1_base->bank[i].rstctl, reg);  in setup_serdes_volt()
207 		reg = in_be32(&serdes1_base->bank[i].rstctl);  in setup_serdes_volt()
209 		out_be32(&serdes1_base->bank[i].rstctl, reg);  in setup_serdes_volt()
216 	for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {  in setup_serdes_volt()
217 		reg = in_be32(&serdes2_base->bank[i].rstctl);  in setup_serdes_volt()
220 		out_be32(&serdes2_base->bank[i].rstctl, reg);  in setup_serdes_volt()
223 		reg = in_be32(&serdes2_base->bank[i].rstctl);  in setup_serdes_volt()
225 		out_be32(&serdes2_base->bank[i].rstctl, reg);  in setup_serdes_volt()
263 	for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {  in setup_serdes_volt()
264 		reg = in_be32(&serdes1_base->bank[i].rstctl);  in setup_serdes_volt()
266 		out_be32(&serdes1_base->bank[i].rstctl, reg);  in setup_serdes_volt()
269 		reg = in_be32(&serdes1_base->bank[i].rstctl);  in setup_serdes_volt()
271 		out_be32(&serdes1_base->bank[i].rstctl, reg);  in setup_serdes_volt()
274 		if (!(cfg_tmp == 0x3 && i == 1)) {  in setup_serdes_volt()
289 	for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {  in setup_serdes_volt()
290 		reg = in_be32(&serdes2_base->bank[i].rstctl);  in setup_serdes_volt()
292 		out_be32(&serdes2_base->bank[i].rstctl, reg);  in setup_serdes_volt()
295 		reg = in_be32(&serdes2_base->bank[i].rstctl);  in setup_serdes_volt()
297 		out_be32(&serdes2_base->bank[i].rstctl, reg);  in setup_serdes_volt()
300 		if (!(cfg_tmp == 0x3 && i == 1)) {  in setup_serdes_volt()
319 	for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {  in setup_serdes_volt()
321 		reg = in_be32(&serdes1_base->bank[i].pllcr0);  in setup_serdes_volt()
323 			reg = in_be32(&serdes1_base->bank[i].rstctl);  in setup_serdes_volt()
325 			out_be32(&serdes1_base->bank[i].rstctl, reg);  in setup_serdes_volt()
328 			reg = in_be32(&serdes1_base->bank[i].rstctl);  in setup_serdes_volt()
331 			out_be32(&serdes1_base->bank[i].rstctl, reg);  in setup_serdes_volt()
339 	for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {  in setup_serdes_volt()
340 		reg = in_be32(&serdes2_base->bank[i].pllcr0);  in setup_serdes_volt()
342 			reg = in_be32(&serdes2_base->bank[i].rstctl);  in setup_serdes_volt()
344 			out_be32(&serdes2_base->bank[i].rstctl, reg);  in setup_serdes_volt()
347 			reg = in_be32(&serdes2_base->bank[i].rstctl);  in setup_serdes_volt()
350 			out_be32(&serdes2_base->bank[i].rstctl, reg);  in setup_serdes_volt()
361 	for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {  in setup_serdes_volt()
362 		reg = in_be32(&serdes1_base->lane[i].gcr0);  in setup_serdes_volt()
364 		out_be32(&serdes1_base->lane[i].gcr0, reg);  in setup_serdes_volt()
371 	for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {  in setup_serdes_volt()
372 		reg = in_be32(&serdes2_base->lane[i].gcr0);  in setup_serdes_volt()
374 		out_be32(&serdes2_base->lane[i].gcr0, reg);  in setup_serdes_volt()
380 	for (i = 0; i < 2; i++) {  in setup_serdes_volt()
381 		reg = in_be32(&serdes1_base->bank[i].pllcr0);  in setup_serdes_volt()
382 		if (!(cfg_tmp & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {  in setup_serdes_volt()
383 			reg = in_be32(&serdes1_base->bank[i].rstctl);  in setup_serdes_volt()
385 			out_be32(&serdes1_base->bank[i].rstctl, reg);  in setup_serdes_volt()
391 	for (i = 0; i < 2; i++) {  in setup_serdes_volt()
392 		reg = in_be32(&serdes2_base->bank[i].pllcr0);  in setup_serdes_volt()
393 		if (!(cfg_tmp & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {  in setup_serdes_volt()
394 			reg = in_be32(&serdes2_base->bank[i].rstctl);  in setup_serdes_volt()
396 			out_be32(&serdes2_base->bank[i].rstctl, reg);  in setup_serdes_volt()