105 		for (i = 0; i < ARRAY_SIZE(final_map); i++) {  in fix_pcie_mmu_map()
106 			switch (final_map[i].phys) {  in fix_pcie_mmu_map()
108 				final_map[i].phys = 0x2000000000ULL;  in fix_pcie_mmu_map()
109 				final_map[i].virt = 0x2000000000ULL;  in fix_pcie_mmu_map()
110 				final_map[i].size = 0x800000000ULL;  in fix_pcie_mmu_map()
113 				final_map[i].phys = 0x2800000000ULL;  in fix_pcie_mmu_map()
114 				final_map[i].virt = 0x2800000000ULL;  in fix_pcie_mmu_map()
115 				final_map[i].size = 0x800000000ULL;  in fix_pcie_mmu_map()
118 				final_map[i].phys = 0x3000000000ULL;  in fix_pcie_mmu_map()
119 				final_map[i].virt = 0x3000000000ULL;  in fix_pcie_mmu_map()
120 				final_map[i].size = 0x800000000ULL;  in fix_pcie_mmu_map()
123 				final_map[i].phys = 0x3800000000ULL;  in fix_pcie_mmu_map()
124 				final_map[i].virt = 0x3800000000ULL;  in fix_pcie_mmu_map()
125 				final_map[i].size = 0x800000000ULL;  in fix_pcie_mmu_map()
152 	mem_map = final_map;  in final_mmu_setup()
155 	for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {  in final_mmu_setup()
161 		switch (final_map[index].virt) {  in final_mmu_setup()
163 			final_map[index].virt = gd->bd->bi_dram[0].start;  in final_mmu_setup()
164 			final_map[index].phys = gd->bd->bi_dram[0].start;  in final_mmu_setup()
165 			final_map[index].size = gd->bd->bi_dram[0].size;  in final_mmu_setup()
170 			final_map[index].virt = gd->bd->bi_dram[1].start;  in final_mmu_setup()
171 			final_map[index].phys = gd->bd->bi_dram[1].start;  in final_mmu_setup()
172 			final_map[index].size = gd->bd->bi_dram[1].size;  in final_mmu_setup()
174 			final_map[index].size = 0;  in final_mmu_setup()
181 			final_map[index].virt = gd->bd->bi_dram[2].start;  in final_mmu_setup()
182 			final_map[index].phys = gd->bd->bi_dram[2].start;  in final_mmu_setup()
183 			final_map[index].size = gd->bd->bi_dram[2].size;  in final_mmu_setup()
185 			final_map[index].size = 0;  in final_mmu_setup()
202 			index = ARRAY_SIZE(final_map) - 2;  in final_mmu_setup()
204 			final_map[index].virt = gd->arch.secure_ram & ~0x3;  in final_mmu_setup()
205 			final_map[index].phys = final_map[index].virt;  in final_mmu_setup()
206 			final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;  in final_mmu_setup()
207 			final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;  in final_mmu_setup()