17 	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;  in spear_late_init()  local
19 	writel(0x80000007, &misc_p->arb_icm_ml1);  in spear_late_init()
20 	writel(0x80000007, &misc_p->arb_icm_ml2);  in spear_late_init()
21 	writel(0x80000007, &misc_p->arb_icm_ml3);  in spear_late_init()
22 	writel(0x80000007, &misc_p->arb_icm_ml4);  in spear_late_init()
23 	writel(0x80000007, &misc_p->arb_icm_ml5);  in spear_late_init()
24 	writel(0x80000007, &misc_p->arb_icm_ml6);  in spear_late_init()
25 	writel(0x80000007, &misc_p->arb_icm_ml7);  in spear_late_init()
26 	writel(0x80000007, &misc_p->arb_icm_ml8);  in spear_late_init()
27 	writel(0x80000007, &misc_p->arb_icm_ml9);  in spear_late_init()
32 	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;  in sel_1v8()  local
35 	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);  in sel_1v8()
38 	writel(ddr2v5, &misc_p->ddr_2v5_compensation);  in sel_1v8()
40 	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);  in sel_1v8()
43 	writel(ddr1v8, &misc_p->ddr_1v8_compensation);  in sel_1v8()
45 	while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE))  in sel_1v8()
51 	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;  in sel_2v5()  local
54 	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);  in sel_2v5()
57 	writel(ddr1v8, &misc_p->ddr_1v8_compensation);  in sel_2v5()
59 	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);  in sel_2v5()
62 	writel(ddr2v5, &misc_p->ddr_2v5_compensation);  in sel_2v5()
64 	while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE))  in sel_2v5()
73 	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;  in plat_ddr_init()  local
78 	ddrpad = readl(&misc_p->ddr_pad);  in plat_ddr_init()
88 	writel(ddrpad, &misc_p->ddr_pad);  in plat_ddr_init()
91 	core3v3 = readl(&misc_p->core_3v3_compensation);  in plat_ddr_init()
94 	writel(core3v3, &misc_p->core_3v3_compensation);  in plat_ddr_init()
96 	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);  in plat_ddr_init()
99 	writel(ddr1v8, &misc_p->ddr_1v8_compensation);  in plat_ddr_init()
101 	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);  in plat_ddr_init()
104 	writel(ddr2v5, &misc_p->ddr_2v5_compensation);  in plat_ddr_init()
106 	if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) {  in plat_ddr_init()
108 		if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL)  in plat_ddr_init()
114 		if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE)  in plat_ddr_init()