336 		mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7),  in clk_cpul_set_rate()
338 		mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(6),  in clk_cpul_set_rate()
340 		mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7),  in clk_cpul_set_rate()
347 	mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(6),  in clk_cpul_set_rate()
349 	mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7),  in clk_cpul_set_rate()
352 	mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(5),  in clk_cpul_set_rate()
354 	mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(6),  in clk_cpul_set_rate()
356 	mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7),  in clk_cpul_set_rate()
384 	mode = (mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(5)) >> 14) &  in rk3588_lpll_get_rate()
390 	m = (mmio_read_32(DSUCRU_BASE + CRU_PLL_CON(16)) >>  in rk3588_lpll_get_rate()
393 	p = (mmio_read_32(DSUCRU_BASE + CRU_PLL_CON(17)) >>  in rk3588_lpll_get_rate()
396 	s = (mmio_read_32(DSUCRU_BASE + CRU_PLL_CON(17)) >>  in rk3588_lpll_get_rate()
399 	k = (mmio_read_32(DSUCRU_BASE + CRU_PLL_CON(18)) >>  in rk3588_lpll_get_rate()
423 	src = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(6)) & 0x0060;  in clk_scmi_cpul_get_rate()
428 		src = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(5)) & 0xc000;  in clk_scmi_cpul_get_rate()
430 		div = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(6)) & 0x1f;  in clk_scmi_cpul_get_rate()
795 	src = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(1)) & 0x1;  in clk_scmi_dsu_get_rate()
799 		src = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(0)) & 0x3000;  in clk_scmi_dsu_get_rate()
801 		div = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(0)) & 0xf80;  in clk_scmi_dsu_get_rate()
826 	mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(5),  in clk_scmi_lpll_disable()
829 	mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(0),  in clk_scmi_lpll_disable()
832 	mmio_write_32(DSUCRU_BASE + CRU_MODE_CON0, CPU_PLL_PATH_SLOWMODE);  in clk_scmi_lpll_disable()
834 	mmio_write_32(DSUCRU_BASE + CRU_PLL_CON(17), CRU_PLL_POWER_DOWN);  in clk_scmi_lpll_disable()
873 		mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7),  in clk_dsu_set_rate()
875 		mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(1),  in clk_dsu_set_rate()
881 	mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(0),  in clk_dsu_set_rate()
884 	mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(0),  in clk_dsu_set_rate()
886 	mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(1),  in clk_dsu_set_rate()
2431 	mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(5), CLKDIV_5BITS_SHF(0U, 9));  in rockchip_clock_init()
2444 	mmio_write_32(DSUCRU_BASE + DSUCRU_CLKSEL_CON(4),  in rockchip_clock_init()
2446 	mmio_write_32(DSUCRU_BASE + DSUCRU_CLKSEL_CON(4),  in rockchip_clock_init()