82 	uint32_t pmu_pd_st0, bus_idle_st0, qch_pwr_st;  member
596 	ddr_data.pmu_pd_st0 = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(0));  in pmu_power_domains_suspend()
601 	if ((ddr_data.pmu_pd_st0 & BIT(PD_PHP)) == 0)  in pmu_power_domains_suspend()
604 	if ((ddr_data.pmu_pd_st0 & BIT(PD_CRYPTO)) == 0)  in pmu_power_domains_suspend()
666 	pmu_set_power_domain(PD_CRYPTO, !!(ddr_data.pmu_pd_st0 & BIT(PD_CRYPTO)));  in pmu_power_domains_resume()
667 	pmu_set_power_domain(PD_SDMMC, !!(ddr_data.pmu_pd_st0 & BIT(PD_SDMMC)));  in pmu_power_domains_resume()
669 	pmu_set_power_domain(PD_NVM, !!(ddr_data.pmu_pd_st0 & BIT(PD_NVM)));  in pmu_power_domains_resume()
670 	pmu_set_power_domain(PD_NVM0, !!(ddr_data.pmu_pd_st0 & BIT(PD_NVM0)));  in pmu_power_domains_resume()
672 	pmu_set_power_domain(PD_SDIO, !!(ddr_data.pmu_pd_st0 & BIT(PD_SDIO)));  in pmu_power_domains_resume()
674 	pmu_set_power_domain(PD_PHP, !!(ddr_data.pmu_pd_st0 & BIT(PD_PHP)));  in pmu_power_domains_resume()
675 	pmu_set_power_domain(PD_PCIE, !!(ddr_data.pmu_pd_st0 & BIT(PD_PCIE)));  in pmu_power_domains_resume()
676 	pmu_set_power_domain(PD_GMAC, !!(ddr_data.pmu_pd_st0 & BIT(PD_GMAC)));  in pmu_power_domains_resume()
678 	pmu_set_power_domain(PD_AUDIO, !!(ddr_data.pmu_pd_st0 & BIT(PD_AUDIO)));  in pmu_power_domains_resume()
680 	pmu_set_power_domain(PD_USB, !!(ddr_data.pmu_pd_st0 & BIT(PD_USB)));  in pmu_power_domains_resume()
682 	pmu_set_power_domain(PD_RGA31, !!(ddr_data.pmu_pd_st0 & BIT(PD_RGA31)));  in pmu_power_domains_resume()
684 	pmu_set_power_domain(PD_VI, !!(ddr_data.pmu_pd_st0 & BIT(PD_VI)));  in pmu_power_domains_resume()
685 	pmu_set_power_domain(PD_ISP1, !!(ddr_data.pmu_pd_st0 & BIT(PD_ISP1)));  in pmu_power_domains_resume()
686 	pmu_set_power_domain(PD_FEC, !!(ddr_data.pmu_pd_st0 & BIT(PD_FEC)));  in pmu_power_domains_resume()
688 	pmu_set_power_domain(PD_VOP, !!(ddr_data.pmu_pd_st0 & BIT(PD_VOP)));  in pmu_power_domains_resume()
690 	pmu_set_power_domain(PD_VO1, !!(ddr_data.pmu_pd_st0 & BIT(PD_VO1)));  in pmu_power_domains_resume()
692 	pmu_set_power_domain(PD_VO0, !!(ddr_data.pmu_pd_st0 & BIT(PD_VO0)));  in pmu_power_domains_resume()
694 	pmu_set_power_domain(PD_VDPU, !!(ddr_data.pmu_pd_st0 & BIT(PD_VDPU)));  in pmu_power_domains_resume()
695 	pmu_set_power_domain(PD_AV1, !!(ddr_data.pmu_pd_st0 & BIT(PD_AV1)));  in pmu_power_domains_resume()
696 	pmu_set_power_domain(PD_RGA30, !!(ddr_data.pmu_pd_st0 & BIT(PD_RGA30)));  in pmu_power_domains_resume()
698 	pmu_set_power_domain(PD_VCODEC, !!(ddr_data.pmu_pd_st0 & BIT(PD_VCODEC)));  in pmu_power_domains_resume()
699 	pmu_set_power_domain(PD_VENC0, !!(ddr_data.pmu_pd_st0 & BIT(PD_VENC0)));  in pmu_power_domains_resume()
700 	pmu_set_power_domain(PD_VENC1, !!(ddr_data.pmu_pd_st0 & BIT(PD_VENC1)));  in pmu_power_domains_resume()
701 	pmu_set_power_domain(PD_RKVDEC0, !!(ddr_data.pmu_pd_st0 & BIT(PD_RKVDEC0)));  in pmu_power_domains_resume()
702 	pmu_set_power_domain(PD_RKVDEC1, !!(ddr_data.pmu_pd_st0 & BIT(PD_RKVDEC1)));  in pmu_power_domains_resume()
704 	pmu_set_power_domain(PD_NPU, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPU)));  in pmu_power_domains_resume()
705 	pmu_set_power_domain(PD_NPUTOP, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPUTOP)));  in pmu_power_domains_resume()
706 	pmu_set_power_domain(PD_NPU2, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPU2)));  in pmu_power_domains_resume()
707 	pmu_set_power_domain(PD_NPU1, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPU1)));  in pmu_power_domains_resume()
709 	pmu_set_power_domain(PD_GPU, !!(ddr_data.pmu_pd_st0 & BIT(PD_GPU)));  in pmu_power_domains_resume()
722 	if ((ddr_data.pmu_pd_st0 & BIT(PD_CRYPTO)) == 0)  in pmu_power_domains_resume()
725 	if ((ddr_data.pmu_pd_st0 & BIT(PD_PHP)) == 0)  in pmu_power_domains_resume()