Lines Matching refs:WITH_16BITS_WMSK
117 WITH_16BITS_WMSK(pmusram_data.dsusgrf_soc_con[i])); in dsu_restore_early()
235 WITH_16BITS_WMSK(clk_save[j])); in clk_gate_con_restore()
238 WITH_16BITS_WMSK(clk_save[j])); in clk_gate_con_restore()
242 WITH_16BITS_WMSK(clk_save[j])); in clk_gate_con_restore()
246 WITH_16BITS_WMSK(clk_save[j])); in clk_gate_con_restore()
1108 WITH_16BITS_WMSK(pmu2_core_pwr_con)); in pmu_sleep_config()
1110 WITH_16BITS_WMSK(pmu2_core_pwr_con)); in pmu_sleep_config()
1112 WITH_16BITS_WMSK(pmu2_clst_idle_con)); in pmu_sleep_config()
1115 WITH_16BITS_WMSK(pmu2_dsu_pwr_con)); in pmu_sleep_config()
1138 WITH_16BITS_WMSK(pmu1_pwr_con)); in pmu_sleep_config()
1142 WITH_16BITS_WMSK(pmu1_cru_pwr_con)); in pmu_sleep_config()
1150 WITH_16BITS_WMSK(pmu1_ddr_pwr_con)); in pmu_sleep_config()
1157 WITH_16BITS_WMSK(pmu1_pll_pd_con[0])); in pmu_sleep_config()
1159 WITH_16BITS_WMSK(pmu1_pll_pd_con[1])); in pmu_sleep_config()
1166 WITH_16BITS_WMSK(pmu2_bus_idle_con[0])); in pmu_sleep_config()
1168 WITH_16BITS_WMSK(pmu2_bus_idle_con[1])); in pmu_sleep_config()
1170 WITH_16BITS_WMSK(pmu2_bus_idle_con[2])); in pmu_sleep_config()
1175 WITH_16BITS_WMSK(pmu2_pwr_gate_con[0])); in pmu_sleep_config()
1177 WITH_16BITS_WMSK(pmu2_pwr_gate_con[1])); in pmu_sleep_config()
1179 WITH_16BITS_WMSK(pmu2_pwr_gate_con[2])); in pmu_sleep_config()
1197 WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con7)); in pmu_sleep_restore()
1199 WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con8)); in pmu_sleep_restore()
1201 WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con9)); in pmu_sleep_restore()
1203 WITH_16BITS_WMSK(ddr_data.pmu1sgrf_soc_con14)); in pmu_sleep_restore()
1206 WITH_16BITS_WMSK(ddr_data.pmu0sgrf_soc_con1)); in pmu_sleep_restore()
1208 WITH_16BITS_WMSK(ddr_data.pmu0grf_soc_con1)); in pmu_sleep_restore()
1226 WITH_16BITS_WMSK(ddr_data.pmu2_vol_gate_con[0])); in pmu_sleep_restore()
1228 WITH_16BITS_WMSK(ddr_data.pmu2_vol_gate_con[1])); in pmu_sleep_restore()
1230 WITH_16BITS_WMSK(ddr_data.pmu2_vol_gate_con[2])); in pmu_sleep_restore()
1233 WITH_16BITS_WMSK(ddr_data.pmu2_submem_gate_sft_con0)); in pmu_sleep_restore()
1236 WITH_16BITS_WMSK(ddr_data.pmu0grf_soc_con3)); in pmu_sleep_restore()
1238 WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con2)); in pmu_sleep_restore()
1241 WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_h)); in pmu_sleep_restore()
1243 WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_l)); in pmu_sleep_restore()
1259 mmio_write_32(PMU0IOC_BASE + 0x8, WITH_16BITS_WMSK(ddr_data.gpio0b_iomux_l)); in soc_sleep_restore()
1280 mmio_write_32(CRU_BASE + 0x280, WITH_16BITS_WMSK(ddr_data.cru_mode_con)); in pm_pll_restore()
1281 mmio_write_32(BUSSCRU_BASE + 0x280, WITH_16BITS_WMSK(ddr_data.busscru_mode_con)); in pm_pll_restore()
1282 mmio_write_32(CRU_BASE + CRU_PLLS_CON(2, 0), WITH_16BITS_WMSK(ddr_data.cpll_con0)); in pm_pll_restore()
1285 mmio_write_32(PMU_BASE + PMU2_BISR_CON(0), WITH_16BITS_WMSK(ddr_data.pmu2_bisr_con0)); in pm_pll_restore()