373 static struct pvtpll_table *rkclk_get_pvtpll_config(struct pvtpll_table *table,  in rkclk_get_pvtpll_config()  argument
380 		if (freq_hz == table[i].rate)  in rkclk_get_pvtpll_config()
381 			return &table[i];  in rkclk_get_pvtpll_config()
1169 	rk_scmi_clock_t *table = NULL;  in rockchip_scmi_get_clock()  local
1172 		table = clock_table[clock_id];  in rockchip_scmi_get_clock()
1173 		if (table == NULL)  in rockchip_scmi_get_clock()
1177 	if ((table != NULL) && (table->is_security == 0))  in rockchip_scmi_get_clock()
1178 		return table;  in rockchip_scmi_get_clock()
1222 	rk_scmi_clock_t *table;  in rockchip_opteed_clk_set_rate()  local
1229 	table = rockchip_scmi_get_clock(0, clk_idx);  in rockchip_opteed_clk_set_rate()
1230 	if (table != NULL)  in rockchip_opteed_clk_set_rate()
1231 		table->clk_ops->set_rate(table, rate);  in rockchip_opteed_clk_set_rate()
1238 	rk_scmi_clock_t *table;  in rockchip_opteed_clk_get_rate()  local
1245 	table = rockchip_scmi_get_clock(0, clk_idx);  in rockchip_opteed_clk_get_rate()
1246 	if (table != NULL)  in rockchip_opteed_clk_get_rate()
1247 		*rate = (uint64_t)table->clk_ops->get_rate(table);  in rockchip_opteed_clk_get_rate()
1253 	rk_scmi_clock_t *table;  in rockchip_opteed_clk_enable()  local
1260 	table = rockchip_scmi_get_clock(0, clk_idx);  in rockchip_opteed_clk_enable()
1261 	if (table != NULL) {  in rockchip_opteed_clk_enable()
1263 			table->clk_ops->set_status(table, enable);  in rockchip_opteed_clk_enable()
1264 			table->enable_count++;  in rockchip_opteed_clk_enable()
1266 			if (table->enable_count == 0)  in rockchip_opteed_clk_enable()
1268 			if (--table->enable_count > 0)  in rockchip_opteed_clk_enable()
1270 			table->clk_ops->set_status(table, enable);  in rockchip_opteed_clk_enable()
1301 static int pvtpll_get_clk(uint64_t clock_id, struct pvtpll_table **table,  in pvtpll_get_clk()  argument
1306 		*table = sys_clk_info.cpul_table;  in pvtpll_get_clk()
1310 		*table = sys_clk_info.cpub_table;  in pvtpll_get_clk()
1314 		*table = sys_clk_info.gpu_table;  in pvtpll_get_clk()
1318 		*table = sys_clk_info.npu_table;  in pvtpll_get_clk()
1325 	if ((*table == NULL) || (*count == 0))  in pvtpll_get_clk()
1333 	struct pvtpll_table *table = NULL;  in pvtpll_volt_sel_adjust()  local
1338 	if (pvtpll_get_clk(clock_id, &table, &count) != 0)  in pvtpll_volt_sel_adjust()
1342 		if (table[i].volt_sel_thr == 0)  in pvtpll_volt_sel_adjust()
1344 		if (volt_sel >= table[i].volt_sel_thr) {  in pvtpll_volt_sel_adjust()
1345 			delta_len = volt_sel - table[i].volt_sel_thr + 1;  in pvtpll_volt_sel_adjust()
1346 			table[i].length += delta_len;  in pvtpll_volt_sel_adjust()
1347 			if (table[i].length > RK3576_PVTPLL_MAX_LENGTH)  in pvtpll_volt_sel_adjust()
1348 				table[i].length = RK3576_PVTPLL_MAX_LENGTH;  in pvtpll_volt_sel_adjust()