Lines Matching refs:PMU2_OFFSET
15 #define PMU2_OFFSET 0x20000 macro
55 #define PMU2_SCU0_PWR_CON (PMU2_OFFSET + 0x0000)
56 #define PMU2_SCU1_PWR_CON (PMU2_OFFSET + 0x0004)
57 #define PMU2_SCU0_PWR_SFTCON (PMU2_OFFSET + 0x0008)
58 #define PMU2_SCU1_PWR_SFTCON (PMU2_OFFSET + 0x000c)
59 #define PMU2_SCU0_AUTO_PWR_CON (PMU2_OFFSET + 0x0010)
60 #define PMU2_SCU1_AUTO_PWR_CON (PMU2_OFFSET + 0x0014)
61 #define PMU2_SCU_PWR_FSM_STATUS (PMU2_OFFSET + 0x0018)
62 #define PMU2_DBG_PWR_CON(i) (PMU2_OFFSET + 0x001c + (i) * 4)
63 #define PMU2_CLUSTER_PWR_ST (PMU2_OFFSET + 0x0024)
64 #define PMU2_CLUSTER0_IDLE_CON (PMU2_OFFSET + 0x0028)
65 #define PMU2_CLUSTER1_IDLE_CON (PMU2_OFFSET + 0x002c)
66 #define PMU2_CLUSTER0_IDLE_SFTCON (PMU2_OFFSET + 0x0030)
67 #define PMU2_CLUSTER1_IDLE_SFTCON (PMU2_OFFSET + 0x0034)
68 #define PMU2_CLUSTER_IDLE_ACK (PMU2_OFFSET + 0x0038)
69 #define PMU2_CLUSTER_IDLE_ST (PMU2_OFFSET + 0x003c)
70 #define PMU2_SCU0_PWRUP_CNT_THRESH (PMU2_OFFSET + 0x0040)
71 #define PMU2_SCU0_PWRDN_CNT_THRESH (PMU2_OFFSET + 0x0044)
72 #define PMU2_SCU0_STABLE_CNT_THRESH (PMU2_OFFSET + 0x0048)
73 #define PMU2_SCU1_PWRUP_CNT_THRESH (PMU2_OFFSET + 0x004c)
74 #define PMU2_SCU1_PWRDN_CNT_THRESH (PMU2_OFFSET + 0x0050)
75 #define PMU2_SCU1_STABLE_CNT_THRESH (PMU2_OFFSET + 0x0054)
76 #define PMU2_CPU_AUTO_PWR_CON(i) (PMU2_OFFSET + 0x0080 + ((i)) * 4)
77 #define PMU2_CPU_PWR_SFTCON(i) (PMU2_OFFSET + 0x00a0 + ((i)) * 4)
78 #define PMU2_CCI_PWR_CON (PMU2_OFFSET + 0x00e0)
79 #define PMU2_CCI_PWR_SFTCON (PMU2_OFFSET + 0x00e4)
80 #define PMU2_CCI_PWR_ST (PMU2_OFFSET + 0x00e8)
81 #define PMU2_CCI_POWER_STATE (PMU2_OFFSET + 0x00ec)
82 #define PMU2_BUS_IDLE_CON(i) (PMU2_OFFSET + 0x0100 + (i) * 4)
83 #define PMU2_BUS_IDLE_SFTCON(i) (PMU2_OFFSET + 0x0110 + (i) * 4)
84 #define PMU2_BUS_IDLE_ACK (PMU2_OFFSET + 0x0120)
85 #define PMU2_BUS_IDLE_ST (PMU2_OFFSET + 0x0128)
86 #define PMU2_NOC_AUTO_CON(i) (PMU2_OFFSET + 0x0130 + (i) * 4)
87 #define PMU2_NOC_AUTO_SFTCON(i) (PMU2_OFFSET + 0x0140 + (i) * 4)
88 #define PMU2_BUS_IDLEACK_BYPASS_CON (PMU2_OFFSET + 0x0150)
89 #define PMU2_PWR_GATE_CON(i) (PMU2_OFFSET + 0x0200 + (i) * 4)
90 #define PMU2_PWR_GATE_SFTCON(i) (PMU2_OFFSET + 0x0210 + (i) * 4)
91 #define PMU2_VOL_GATE_SFTCON(i) (PMU2_OFFSET + 0x0220 + (i) * 4)
92 #define PMU2_PWR_GATE_ST (PMU2_OFFSET + 0x0230)
93 #define PMU2_PWR_GATE_FSM (PMU2_OFFSET + 0x0238)
94 #define PMU2_PD_DWN_ACK_STATE(i) (PMU2_OFFSET + 0x0240 + (i) * 4)
95 #define PMU2_PD_DWN_LC_ACK_STATE(i) (PMU2_OFFSET + 0x0248 + (i) * 4)
96 #define PMU2_PD_DWN_MEM_ACK_STATE(i) (PMU2_OFFSET + 0x0250 + (i) * 4)
97 #define PMU2_PWR_UP_C0_STABLE_CON(i) (PMU2_OFFSET + 0x0260 + (i) * 4)
98 #define PMU2_PWR_DWN_C0_STABLE_CON(i) (PMU2_OFFSET + 0x0270 + (i) * 4)
99 #define PMU2_PWR_STABLE_C0_CNT_THRES (PMU2_OFFSET + 0x027c)
100 #define PMU2_FAST_POWER_CON (PMU2_OFFSET + 0x0284)
101 #define PMU2_FAST_PWRUP_CNT_THRESH_0 (PMU2_OFFSET + 0x0288)
102 #define PMU2_FAST_PWRDN_CNT_THRESH_0 (PMU2_OFFSET + 0x028c)
103 #define PMU2_FAST_PWRUP_CNT_THRESH_1 (PMU2_OFFSET + 0x0290)
104 #define PMU2_FAST_PWRDN_CNT_THRESH_1 (PMU2_OFFSET + 0x0294)
105 #define PMU2_FAST_PWRUP_CNT_THRESH_2 (PMU2_OFFSET + 0x0298)
106 #define PMU2_FAST_PWRDN_CNT_THRESH_2 (PMU2_OFFSET + 0x029c)
107 #define PMU2_MEM_PWR_GATE_SFTCON(i) (PMU2_OFFSET + 0x0300)
108 #define PMU2_SUBMEM_PWR_GATE_SFTCON(i) (PMU2_OFFSET + 0x0310)
109 #define PMU2_SUBMEM_PWR_ACK_BYPASS_SFTCON(i) (PMU2_OFFSET + 0x0320)
110 #define PMU2_SUBMEM_PWR_GATE_STATUS (PMU2_OFFSET + 0x0328)
111 #define PMU2_QCHANNEL_PWR_CON0 (PMU2_OFFSET + 0x0400)
112 #define PMU2_QCHANNEL_PWR_SFTCON0 (PMU2_OFFSET + 0x0404)
113 #define PMU2_QCHANNEL_STATUS0 (PMU2_OFFSET + 0x0408)
114 #define PMU2_C0_PWRACK_BYPASS_CON(i) (PMU2_OFFSET + 0x0380 + (i) * 4)
115 #define PMU2_C1_PWRACK_BYPASS_CON(i) (PMU2_OFFSET + 0x0390 + (i) * 4)
116 #define PMU2_C2_PWRACK_BYPASS_CON(i) (PMU2_OFFSET + 0x03a0 + (i) * 4)
117 #define PMU2_DEBUG_INFO_SEL (PMU2_OFFSET + 0x03f0)
118 #define PMU2_BISR_GLB_CON (PMU2_OFFSET + 0x500)
119 #define PMU2_BISR_TIMEOUT_THRES (PMU2_OFFSET + 0x504)
120 #define PMU2_BISR_PDGEN_CON(i) (PMU2_OFFSET + 0x510 + (i) * 4)
121 #define PMU2_BISR_PDGEN_SFTCON(i) (PMU2_OFFSET + 0x520 + (i) * 4)
122 #define PMU2_BISR_PDGDONE_CON(i) (PMU2_OFFSET + 0x530 + (i) * 4)
123 #define PMU2_BISR_PDGINIT_CON(i) (PMU2_OFFSET + 0x540 + (i) * 4)
124 #define PMU2_BISR_PDGDONE_STATUS(i) (PMU2_OFFSET + 0x550 + (i) * 4)
125 #define PMU2_BISR_PDGCEDIS_STATUS(i) (PMU2_OFFSET + 0x560 + (i) * 4)
126 #define PMU2_BISR_PWR_REPAIR_STATUS(i) (PMU2_OFFSET + 0x570 + (i) * 4)