Lines Matching refs:PMU1_OFFSET
14 #define PMU1_OFFSET 0x10000 macro
28 #define PMU1_VERSION_ID (PMU1_OFFSET + 0x0000)
29 #define PMU1_PWR_CON (PMU1_OFFSET + 0x0004)
30 #define PMU1_PWR_FSM (PMU1_OFFSET + 0x0008)
31 #define PMU1_INT_MASK_CON (PMU1_OFFSET + 0x000c)
32 #define PMU1_WAKEUP_INT_CON (PMU1_OFFSET + 0x0010)
33 #define PMU1_WAKEUP_INT_ST (PMU1_OFFSET + 0x0014)
34 #define PMU1_DDR_PWR_CON(i) (PMU1_OFFSET + 0x0100 + (i) * 4)
35 #define PMU1_DDR_PWR_SFTCON(i) (PMU1_OFFSET + 0x0110 + (i) * 4)
36 #define PMU1_DDR_AXIPWR_CON(i) (PMU1_OFFSET + 0x0120 + (i) * 4)
37 #define PMU1_DDR_AXIPWR_SFTCON(i) (PMU1_OFFSET + 0x0130 + (i) * 4)
38 #define PMU1_DDR_PWR_FSM (PMU1_OFFSET + 0x0140)
39 #define PMU1_DDR_PWR_ST (PMU1_OFFSET + 0x0144)
40 #define PMU1_DDR_AXIPWR_ST (PMU1_OFFSET + 0x0148)
41 #define PMU1_CRU_PWR_CON(i) (PMU1_OFFSET + 0x0200 + (i) * 4)
42 #define PMU1_CRU_PWR_SFTCON(i) (PMU1_OFFSET + 0x0208 + (i) * 4)
43 #define PMU1_CRU_PWR_FSM (PMU1_OFFSET + 0x0210)
44 #define PMU1_PLLPD_CON(i) (PMU1_OFFSET + 0x0220 + (i) * 4)
45 #define PMU1_PLLPD_SFTCON(i) (PMU1_OFFSET + 0x0228 + (i) * 4)
46 #define PMU1_STABLE_CNT_THRESH (PMU1_OFFSET + 0x0300)
47 #define PMU1_OSC_STABLE_CNT_THRESH (PMU1_OFFSET + 0x0304)
48 #define PMU1_WAKEUP_RST_CLR_CNT_THRESH (PMU1_OFFSET + 0x0308)
49 #define PMU1_PLL_LOCK_CNT_THRESH (PMU1_OFFSET + 0x030c)
50 #define PMU1_WAKEUP_TIMEOUT_THRESH (PMU1_OFFSET + 0x0310)
51 #define PMU1_PWM_SWITCH_CNT_THRESH (PMU1_OFFSET + 0x0314)
52 #define PMU1_SLEEP_CNT_THRESH (PMU1_OFFSET + 0x0318)
53 #define PMU1_INFO_TX_CON (PMU1_OFFSET + 0x0400)