25 #define PMU0_DDR_RET_CON(i)		(0x0020 + (i) * 4)  argument
34 #define PMU1_DDR_PWR_CON(i)		(PMU1_OFFSET + 0x0100 + (i) * 4)  argument
35 #define PMU1_DDR_PWR_SFTCON(i)		(PMU1_OFFSET + 0x0110 + (i) * 4)  argument
36 #define PMU1_DDR_AXIPWR_CON(i)		(PMU1_OFFSET + 0x0120 + (i) * 4)  argument
37 #define PMU1_DDR_AXIPWR_SFTCON(i)	(PMU1_OFFSET + 0x0130 + (i) * 4)  argument
41 #define PMU1_CRU_PWR_CON(i)		(PMU1_OFFSET + 0x0200 + (i) * 4)  argument
42 #define PMU1_CRU_PWR_SFTCON(i)		(PMU1_OFFSET + 0x0208 + (i) * 4)  argument
44 #define PMU1_PLLPD_CON(i)		(PMU1_OFFSET + 0x0220 + (i) * 4)  argument
45 #define PMU1_PLLPD_SFTCON(i)		(PMU1_OFFSET + 0x0228 + (i) * 4)  argument
62 #define PMU2_DBG_PWR_CON(i)		(PMU2_OFFSET + 0x001c + (i) * 4)  argument
76 #define PMU2_CPU_AUTO_PWR_CON(i)	(PMU2_OFFSET + 0x0080 + ((i)) * 4)  argument
77 #define PMU2_CPU_PWR_SFTCON(i)		(PMU2_OFFSET + 0x00a0 + ((i)) * 4)  argument
82 #define PMU2_BUS_IDLE_CON(i)		(PMU2_OFFSET + 0x0100 + (i) * 4)  argument
83 #define PMU2_BUS_IDLE_SFTCON(i)		(PMU2_OFFSET + 0x0110 + (i) * 4)  argument
86 #define PMU2_NOC_AUTO_CON(i)		(PMU2_OFFSET + 0x0130 + (i) * 4)  argument
87 #define PMU2_NOC_AUTO_SFTCON(i)		(PMU2_OFFSET + 0x0140 + (i) * 4)  argument
89 #define PMU2_PWR_GATE_CON(i)		(PMU2_OFFSET + 0x0200 + (i) * 4)  argument
90 #define PMU2_PWR_GATE_SFTCON(i)		(PMU2_OFFSET + 0x0210 + (i) * 4)  argument
91 #define PMU2_VOL_GATE_SFTCON(i)		(PMU2_OFFSET + 0x0220 + (i) * 4)  argument
94 #define PMU2_PD_DWN_ACK_STATE(i)	(PMU2_OFFSET + 0x0240 + (i) * 4)  argument
95 #define PMU2_PD_DWN_LC_ACK_STATE(i)	(PMU2_OFFSET + 0x0248 + (i) * 4)  argument
96 #define PMU2_PD_DWN_MEM_ACK_STATE(i)	(PMU2_OFFSET + 0x0250 + (i) * 4)  argument
97 #define PMU2_PWR_UP_C0_STABLE_CON(i)	(PMU2_OFFSET + 0x0260 + (i) * 4)  argument
98 #define PMU2_PWR_DWN_C0_STABLE_CON(i)	(PMU2_OFFSET + 0x0270 + (i) * 4)  argument
107 #define PMU2_MEM_PWR_GATE_SFTCON(i)	(PMU2_OFFSET + 0x0300)  argument
108 #define PMU2_SUBMEM_PWR_GATE_SFTCON(i)	(PMU2_OFFSET + 0x0310)  argument
109 #define PMU2_SUBMEM_PWR_ACK_BYPASS_SFTCON(i)	(PMU2_OFFSET + 0x0320)  argument
114 #define PMU2_C0_PWRACK_BYPASS_CON(i)	(PMU2_OFFSET + 0x0380 + (i) * 4)  argument
115 #define PMU2_C1_PWRACK_BYPASS_CON(i)	(PMU2_OFFSET + 0x0390 + (i) * 4)  argument
116 #define PMU2_C2_PWRACK_BYPASS_CON(i)	(PMU2_OFFSET + 0x03a0 + (i) * 4)  argument
120 #define PMU2_BISR_PDGEN_CON(i)		(PMU2_OFFSET + 0x510 + (i) * 4)  argument
121 #define PMU2_BISR_PDGEN_SFTCON(i)	(PMU2_OFFSET + 0x520 + (i) * 4)  argument
122 #define PMU2_BISR_PDGDONE_CON(i)	(PMU2_OFFSET + 0x530 + (i) * 4)  argument
123 #define PMU2_BISR_PDGINIT_CON(i)	(PMU2_OFFSET + 0x540 + (i) * 4)  argument
124 #define PMU2_BISR_PDGDONE_STATUS(i)	(PMU2_OFFSET + 0x550 + (i) * 4)  argument
125 #define PMU2_BISR_PDGCEDIS_STATUS(i)	(PMU2_OFFSET + 0x560 + (i) * 4)  argument
126 #define PMU2_BISR_PWR_REPAIR_STATUS(i)	(PMU2_OFFSET + 0x570 + (i) * 4)  argument
129 #define PMU1CRU_CLKSEL_CON(i)		((i) * 0x4 + 0x300)  argument
131 #define PMU1CRU_CLKGATE_CON(i)		((i) * 0x4 + 0x800)  argument
133 #define PMU1CRU_SOFTRST_CON(i)		((i) * 0x4 + 0xa00)  argument
139 #define PMU1SCRU_CLKSEL_CON(i)		((i) * 0x4 + 0x4000)  argument
141 #define PMU1SCRU_CLKGATE_CON(i)		((i) * 0x4 + 0x4028)  argument
143 #define PMU1SCRU_SOFTRST_CON(i)		((i) * 0x4 + 0x4050)  argument
147 #define PMU0GRF_SOC_CON(i)		((i) * 4)  argument
148 #define PMU0GRF_IO_RET_CON(i)		(0x20 + (i) * 4)  argument
149 #define PMU0GRF_OS_REG(i)		((i) * 4)  argument
152 #define PMU1GRF_SOC_CON(i)		((i) * 4)  argument
154 #define PMU1GRF_MEM_CON(i)		(0x80 + (i) * 4)  argument
155 #define PMU1GRF_OS_REG(i)		(0x200 + (i) * 4)  argument