379 			      WITH_16BITS_WMSK(clk_save[j]));  in clk_gate_con_restore()
383 			      WITH_16BITS_WMSK(clk_save[j]));  in clk_gate_con_restore()
387 			      WITH_16BITS_WMSK(clk_save[j]));  in clk_gate_con_restore()
391 			      WITH_16BITS_WMSK(clk_save[j]));  in clk_gate_con_restore()
395 			      WITH_16BITS_WMSK(clk_save[j]));  in clk_gate_con_restore()
399 			      WITH_16BITS_WMSK(clk_save[j]));  in clk_gate_con_restore()
594 		      WITH_16BITS_WMSK(ddr_data.ddrgrf_cha_con2));  in ddr_sleep_config_restore()
596 		      WITH_16BITS_WMSK(ddr_data.ddrgrf_chb_con2));  in ddr_sleep_config_restore()
750 	mmio_write_32(PMU_BASE + PMU1_PWR_CON, WITH_16BITS_WMSK(pmu1_pwr_con));  in pmu_sleep_config()
753 	mmio_write_32(PMU_BASE + PMU1_CRU_PWR_CON(0), WITH_16BITS_WMSK(pmu1cru_pwr_con));  in pmu_sleep_config()
757 	mmio_write_32(PMU_BASE + PMU1_DDR_PWR_CON(0), WITH_16BITS_WMSK(pmu1_ddr_pwr_con));  in pmu_sleep_config()
758 	mmio_write_32(PMU_BASE + PMU1_DDR_PWR_CON(1), WITH_16BITS_WMSK(pmu1_ddr_pwr_con));  in pmu_sleep_config()
763 	mmio_write_32(PMU_BASE + PMU1_PLLPD_CON(0), WITH_16BITS_WMSK(pmu1_pll_pd_con));  in pmu_sleep_config()
766 	mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(0), WITH_16BITS_WMSK(pmu2_bus_idle_con[0]));  in pmu_sleep_config()
767 	mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(1), WITH_16BITS_WMSK(pmu2_bus_idle_con[1]));  in pmu_sleep_config()
770 	mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(0), WITH_16BITS_WMSK(pmu2_pwr_gt_con[0]));  in pmu_sleep_config()
771 	mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(1), WITH_16BITS_WMSK(pmu2_pwr_gt_con[1]));  in pmu_sleep_config()
817 		      WITH_16BITS_WMSK(ddr_data.pmu2_fast_pwr_con));  in pmu_sleep_restore()
819 		      WITH_16BITS_WMSK(ddr_data.pmu2_bisr_glb_con));  in pmu_sleep_restore()
822 		      WITH_16BITS_WMSK(ddr_data.pmu2_c0_ack_sel_con0));  in pmu_sleep_restore()
824 		      WITH_16BITS_WMSK(ddr_data.pmu2_c1_ack_sel_con0));  in pmu_sleep_restore()
826 		      WITH_16BITS_WMSK(ddr_data.pmu2_c2_ack_sel_con0));  in pmu_sleep_restore()
829 		      WITH_16BITS_WMSK(ddr_data.pmu0grf_soc_con5));  in pmu_sleep_restore()
879 		      WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_l));  in soc_sleep_restore()
881 		      WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_h));  in soc_sleep_restore()
883 		      WITH_16BITS_WMSK(ddr_data.gpio0b_iomux_l));  in soc_sleep_restore()
886 		      WITH_16BITS_WMSK(ddr_data.pmu0grf_soc_con1));  in soc_sleep_restore()
888 		      WITH_16BITS_WMSK(ddr_data.pmu0grf_soc_con0));  in soc_sleep_restore()
907 	mmio_write_32(CRU_BASE + 0x280, WITH_16BITS_WMSK(ddr_data.cru_mode_con));  in pm_pll_restore()
909 		      WITH_16BITS_WMSK(ddr_data.secure_cru_mode));  in pm_pll_restore()