82 	configs->low_power[ch].pcl_pd = mmio_read_32(DDRPHY_BASE_CH(0) + LP_CON0) & PCL_PD;  in exit_low_power()
86 	configs->low_power[ch].pwrctl = mmio_read_32(UMCTL_BASE_CH(ch) + DDRCTL_PWRCTL);  in exit_low_power()
95 	configs->low_power[ch].grf_ddr_con6 =  in exit_low_power()
100 	configs->low_power[ch].grf_ddr_con0 =  in exit_low_power()
109 	configs->low_power[ch].grf_ddr_con1 =  in exit_low_power()
113 	configs->low_power[ch].hwlp_0 = mmio_read_32(HWLP_BASE_CH(ch) + 0x0);  in exit_low_power()
115 	configs->low_power[ch].hwlp_c = mmio_read_32(HWLP_BASE_CH(ch) + 0xc);  in exit_low_power()
119 	configs->low_power[ch].grf_ddrphy_con0 =  in exit_low_power()
124 	configs->low_power[ch].clkgatectl =  in exit_low_power()
127 	configs->low_power[ch].dfi_lp_mode_apb =  in exit_low_power()
134 	if (configs->low_power[ch].dfi_lp_mode_apb != 0)  in resume_low_power()
139 			   0x3f, configs->low_power[ch].clkgatectl & 0x3f);  in resume_low_power()
143 		      (0xff7ful << 16) | configs->low_power[ch].grf_ddr_con6);  in resume_low_power()
145 	mmio_write_32(HWLP_BASE_CH(ch) + 0xc, configs->low_power[ch].hwlp_c);  in resume_low_power()
146 	mmio_write_32(HWLP_BASE_CH(ch) + 0x0, configs->low_power[ch].hwlp_0);  in resume_low_power()
150 		      (0x1f00ul << 16) | configs->low_power[ch].grf_ddr_con0);  in resume_low_power()
158 		      (0x90e6ul << 16) | configs->low_power[ch].grf_ddr_con1);  in resume_low_power()
162 		      BIT(14 + 16) | configs->low_power[ch].grf_ddrphy_con0);  in resume_low_power()
165 	mmio_write_32(UMCTL_BASE_CH(ch) + DDRCTL_PWRCTL, configs->low_power[ch].pwrctl);  in resume_low_power()
168 	if (configs->low_power[ch].pcl_pd != 0)  in resume_low_power()