39 struct rk3399_dram_status {  struct
54 static struct rk3399_dram_status rk3399_dram_status;  argument
1398 	for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) {  in gen_rk3399_set_odt()
1806 	uint32_t ch_cnt = rk3399_dram_status.timing_config.ch_cnt;  in dram_low_power_config()
1807 	uint32_t dram_type = rk3399_dram_status.timing_config.dram_type;  in dram_low_power_config()
1841 			     &rk3399_dram_status.drv_odt_lp_cfg);  in dram_dfs_init()
1842 	sdram_timing_cfg_init(&rk3399_dram_status.timing_config,  in dram_dfs_init()
1844 			      &rk3399_dram_status.drv_odt_lp_cfg);  in dram_dfs_init()
1849 	rk3399_dram_status.index_freq[0] = trefi0 * 10 / 39;  in dram_dfs_init()
1850 	rk3399_dram_status.index_freq[1] = trefi1 * 10 / 39;  in dram_dfs_init()
1851 	rk3399_dram_status.current_index =  in dram_dfs_init()
1853 	if (rk3399_dram_status.timing_config.dram_type == DDR3) {  in dram_dfs_init()
1854 		rk3399_dram_status.index_freq[0] /= 2;  in dram_dfs_init()
1855 		rk3399_dram_status.index_freq[1] /= 2;  in dram_dfs_init()
1858 		rk3399_dram_status.index_freq[rk3399_dram_status.current_index];  in dram_dfs_init()
1860 	rk3399_dram_status.boot_freq = boot_freq;  in dram_dfs_init()
1861 	rk3399_dram_status.index_freq[rk3399_dram_status.current_index] =  in dram_dfs_init()
1863 	rk3399_dram_status.index_freq[(rk3399_dram_status.current_index + 1) &  in dram_dfs_init()
1865 	rk3399_dram_status.low_power_stat = 0;  in dram_dfs_init()
1897 				   rk3399_dram_status.current_index << 8);  in dram_dfs_init()
1917 	struct drv_odt_lp_config *lp_cfg = &rk3399_dram_status.drv_odt_lp_cfg;  in dram_set_odt_pd()
1918 	uint32_t *low_power = &rk3399_dram_status.low_power_stat;  in dram_set_odt_pd()
1921 	dram_type = rk3399_dram_status.timing_config.dram_type;  in dram_set_odt_pd()
1922 	ch_count = rk3399_dram_status.timing_config.ch_cnt;  in dram_set_odt_pd()
1930 	rk3399_dram_status.timing_config.odt = arg2 & 0x1;  in dram_set_odt_pd()
1947 		if (rk3399_dram_status.timing_config.ch_cnt == 2)  in dram_set_odt_pd()
1985 	rk3399_dram_status.timing_config.freq = mhz;  in prepare_ddr_timing()
1988 		rk3399_dram_status.timing_config.dllbp = 1;  in prepare_ddr_timing()
1990 		rk3399_dram_status.timing_config.dllbp = 0;  in prepare_ddr_timing()
1992 	if (rk3399_dram_status.timing_config.odt == 1)  in prepare_ddr_timing()
1995 	index = (rk3399_dram_status.current_index + 1) & 0x1;  in prepare_ddr_timing()
2001 	dram_get_parameter(&rk3399_dram_status.timing_config, &dram_timing);  in prepare_ddr_timing()
2002 	gen_rk3399_ctl_params(&rk3399_dram_status.timing_config,  in prepare_ddr_timing()
2004 	gen_rk3399_pi_params(&rk3399_dram_status.timing_config,  in prepare_ddr_timing()
2006 	gen_rk3399_phy_params(&rk3399_dram_status.timing_config,  in prepare_ddr_timing()
2007 			      &rk3399_dram_status.drv_odt_lp_cfg,  in prepare_ddr_timing()
2009 	rk3399_dram_status.index_freq[index] = mhz;  in prepare_ddr_timing()
2020 	    rk3399_dram_status.index_freq[rk3399_dram_status.current_index])  in ddr_set_rate()
2027 	gen_rk3399_enable_training(rk3399_dram_status.timing_config.ch_cnt,  in ddr_set_rate()
2041 	if (rk3399_dram_status.timing_config.odt == 0)  in ddr_set_rate()
2044 	rk3399_dram_status.current_index = ddr_index;  in ddr_set_rate()
2045 	low_power = rk3399_dram_status.low_power_stat;  in ddr_set_rate()
2048 	gen_rk3399_disable_training(rk3399_dram_status.timing_config.ch_cnt);  in ddr_set_rate()
2065 		rk3399_dram_status.index_freq[rk3399_dram_status.current_index];  in ddr_prepare_for_sys_suspend()
2074 		rk3399_dram_status.low_power_stat;  in ddr_prepare_for_sys_suspend()
2075 	rk3399_suspend_status.odt = rk3399_dram_status.timing_config.odt;  in ddr_prepare_for_sys_suspend()
2076 	rk3399_dram_status.low_power_stat = 0;  in ddr_prepare_for_sys_suspend()
2077 	rk3399_dram_status.timing_config.odt = 1;  in ddr_prepare_for_sys_suspend()
2078 	if (mhz != rk3399_dram_status.boot_freq)  in ddr_prepare_for_sys_suspend()
2079 		ddr_set_rate(rk3399_dram_status.boot_freq * 1000 * 1000);  in ddr_prepare_for_sys_suspend()
2086 	prepare_ddr_timing(rk3399_dram_status.boot_freq);  in ddr_prepare_for_sys_suspend()
2096 	rk3399_dram_status.current_index =  in ddr_prepare_for_sys_resume()
2098 	rk3399_dram_status.low_power_stat =  in ddr_prepare_for_sys_resume()
2100 	rk3399_dram_status.timing_config.odt = rk3399_suspend_status.odt;  in ddr_prepare_for_sys_resume()
2107 	    rk3399_dram_status.index_freq[rk3399_dram_status.current_index]) {  in ddr_prepare_for_sys_resume()
2112 	gen_rk3399_set_odt(rk3399_dram_status.timing_config.odt);  in ddr_prepare_for_sys_resume()
2113 	resume_low_power(rk3399_dram_status.low_power_stat);  in ddr_prepare_for_sys_resume()