Lines Matching refs:ptiming_config
180 static void sdram_timing_cfg_init(struct timing_related_config *ptiming_config, in sdram_timing_cfg_init() argument
187 ptiming_config->dram_info[i].speed_rate = DDR3_DEFAULT; in sdram_timing_cfg_init()
188 ptiming_config->dram_info[i].cs_cnt = sdram_params->ch[i].rank; in sdram_timing_cfg_init()
190 ptiming_config->dram_info[i].per_die_capability[j] = in sdram_timing_cfg_init()
194 ptiming_config->dram_type = sdram_params->dramtype; in sdram_timing_cfg_init()
195 ptiming_config->ch_cnt = sdram_params->num_channels; in sdram_timing_cfg_init()
198 ptiming_config->bl = ddr3_default_config.bl; in sdram_timing_cfg_init()
199 ptiming_config->ap = ddr3_default_config.ap; in sdram_timing_cfg_init()
202 ptiming_config->bl = lpddr3_default_config.bl; in sdram_timing_cfg_init()
203 ptiming_config->ap = lpddr3_default_config.ap; in sdram_timing_cfg_init()
206 ptiming_config->bl = lpddr4_default_config.bl; in sdram_timing_cfg_init()
207 ptiming_config->ap = lpddr4_default_config.ap; in sdram_timing_cfg_init()
208 ptiming_config->rdbi = 0; in sdram_timing_cfg_init()
209 ptiming_config->wdbi = 0; in sdram_timing_cfg_init()
215 ptiming_config->dramds = drv_config->dram_side_drv; in sdram_timing_cfg_init()
216 ptiming_config->dramodt = drv_config->dram_side_dq_odt; in sdram_timing_cfg_init()
217 ptiming_config->caodt = drv_config->dram_side_ca_odt; in sdram_timing_cfg_init()
218 ptiming_config->odt = (mmio_read_32(PHY_REG(0, 5)) >> 16) & 0x1; in sdram_timing_cfg_init()