195 	ptiming_config->ch_cnt = sdram_params->num_channels;  in sdram_timing_cfg_init()
492 	for (i = 0; i < timing_config->ch_cnt; i++) {  in gen_rk3399_ctl_params_f0()
744 	for (i = 0; i < timing_config->ch_cnt; i++) {  in gen_rk3399_ctl_params_f1()
988 static void gen_rk3399_enable_training(uint32_t ch_cnt, uint32_t nmhz)  in gen_rk3399_enable_training()  argument
997 		for (i = 0; i < ch_cnt; i++) {  in gen_rk3399_enable_training()
1004 static void gen_rk3399_disable_training(uint32_t ch_cnt)  in gen_rk3399_disable_training()  argument
1008 	for (i = 0; i < ch_cnt; i++) {  in gen_rk3399_disable_training()
1031 	for (i = 0; i < timing_config->ch_cnt; i++) {  in gen_rk3399_pi_params_f0()
1209 	for (i = 0; i < timing_config->ch_cnt; i++) {  in gen_rk3399_pi_params_f1()
1398 	for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) {  in gen_rk3399_set_odt()
1511 	for (i = 0; i < timing_config->ch_cnt; i++) {  in gen_rk3399_phy_params()
1806 	uint32_t ch_cnt = rk3399_dram_status.timing_config.ch_cnt;  in dram_low_power_config()  local
1814 	for (i = 0; i < ch_cnt; i++)  in dram_low_power_config()
1820 	if (ch_cnt == 2) {  in dram_low_power_config()
1922 	ch_count = rk3399_dram_status.timing_config.ch_cnt;  in dram_set_odt_pd()
1947 		if (rk3399_dram_status.timing_config.ch_cnt == 2)  in dram_set_odt_pd()
2027 	gen_rk3399_enable_training(rk3399_dram_status.timing_config.ch_cnt,  in ddr_set_rate()
2048 	gen_rk3399_disable_training(rk3399_dram_status.timing_config.ch_cnt);  in ddr_set_rate()