127 	plls_con[pll_id][0] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 0));  in plls_suspend()
128 	plls_con[pll_id][1] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 1));  in plls_suspend()
129 	plls_con[pll_id][2] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 2));  in plls_suspend()
130 	plls_con[pll_id][3] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 3));  in plls_suspend()
132 	mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_SLOW_BITS);  in plls_suspend()
133 	mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_BYPASS);  in plls_suspend()
147 	mmio_write_32(CRU_BASE + PLL_CONS(ABPLL_ID, 3),  in plls_resume()
149 	mmio_write_32(CRU_BASE + PLL_CONS(ALPLL_ID, 3),  in plls_resume()
151 	mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3),  in plls_resume()
153 	mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3),  in plls_resume()
155 	mmio_write_32(CRU_BASE + PLL_CONS(NPLL_ID, 3),  in plls_resume()
175 	mmio_write_32(CRU_BASE + PLL_CONS(ABPLL_ID, 3),  in pm_plls_resume()
177 	mmio_write_32(CRU_BASE + PLL_CONS(ALPLL_ID, 3),  in pm_plls_resume()
179 	mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3),  in pm_plls_resume()
181 	mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3),  in pm_plls_resume()
183 	mmio_write_32(CRU_BASE + PLL_CONS(NPLL_ID, 3),  in pm_plls_resume()
191 	mmio_write_32(CRU_BASE + PLL_CONS((GPLL_ID), 3), PLL_SLOW_BITS);  in rockchip_soc_soft_reset()
192 	mmio_write_32(CRU_BASE + PLL_CONS((CPLL_ID), 3), PLL_SLOW_BITS);  in rockchip_soc_soft_reset()
193 	mmio_write_32(CRU_BASE + PLL_CONS((NPLL_ID), 3), PLL_SLOW_BITS);  in rockchip_soc_soft_reset()
194 	mmio_write_32(CRU_BASE + PLL_CONS((ABPLL_ID), 3), PLL_SLOW_BITS);  in rockchip_soc_soft_reset()
195 	mmio_write_32(CRU_BASE + PLL_CONS((ALPLL_ID), 3), PLL_SLOW_BITS);  in rockchip_soc_soft_reset()