Lines Matching refs:w1
191 str w1, [x2, #DCFG_BOOTLOCPTRL_OFFSET]
195 str w1, [x2, #DCFG_BOOTLOCPTRH_OFFSET]
245 ldr w1, [x1, #DCFG_COREDISABLEDSR_OFFSET]
248 and w0, w1, w0
414 mvn w1, wzr
415 str w1, [x5, #GICR_ICPENDR0_OFFSET]
498 mov w1, #GICR_ICENABLER0_SGI15
499 str w1, [x4, #GICR_ICENABLER0_OFFSET]
569 ldr w1, =DCFG_DEVDISR1_SEC
570 str w1, [x2, x0]
572 ldr w1, =DCFG_DEVDISR3_QBMAIN
573 str w1, [x2, x0]
575 ldr w1, =DCFG_DEVDISR4_SPI_QSPI
576 str w1, [x2, x0]
580 mov w1, #0x1
581 str w1, [x0]
609 ldr w1, [x3, #PMU_PCPW20SR_OFFSET]
610 cmp w1, #PMU_IDLE_CORE_MASK
613 mov w1, #PMU_IDLE_CLUSTER_MASK
614 str w1, [x3, #PMU_CLAINACTSETR_OFFSET]
617 ldr w1, [x3, #PMU_PCPW20SR_OFFSET]
618 cmp w1, #PMU_IDLE_CORE_MASK
621 mov w1, #PMU_FLUSH_CLUSTER_MASK
622 str w1, [x3, #PMU_CLL2FLUSHSETR_OFFSET]
625 ldr w1, [x3, #PMU_CLL2FLUSHSR_OFFSET]
626 cmp w1, #PMU_FLUSH_CLUSTER_MASK
629 mov w1, #PMU_FLUSH_CLUSTER_MASK
630 str w1, [x3, #PMU_CLSL2FLUSHCLRR_OFFSET]
632 mov w1, #PMU_FLUSH_CLUSTER_MASK
633 str w1, [x3, #PMU_CLSINACTSETR_OFFSET]
658 ldr w1, =PMU_POWMGTCSR_VAL
659 str w1, [x3, x0]
1629 ldr w1, [x0, #DCFG_COREDISR_OFFSET]
1630 orr w1, w1, #CLUSTER_3_CORES_MASK
1631 str w1, [x0, #DCFG_COREDISR_OFFSET]
1697 str w1, [x2, x0]
1709 ldr w1, [x2, x0]
1710 mov w0, w1
1724 mov w1, #31
1725 sub w0, w1, w0
1728 mov w1, wzr
1731 orr w1, w1, #1
1736 orr w0, w1, w0, lsl #8
1749 clz w1, w0
1751 sub w2, w2, w1
1777 clz w1, w0
1779 sub w2, w2, w1
1802 str w1, [x2, x0]