Lines Matching refs:str
191 str w1, [x2, #DCFG_BOOTLOCPTRL_OFFSET]
195 str w1, [x2, #DCFG_BOOTLOCPTRH_OFFSET]
212 str w0, [x1, #CORE_HOLD_OFFSET]
220 str w2, [x1, #BRR_OFFSET]
269 str w2, [x5, #GICD_CTLR_OFFSET]
357 str w3, [x5, #GICR_ICENABLER0_OFFSET]
375 str w4, [x5, #GICR_IGROUPR0_OFFSET]
380 str w3, [x5, #GICR_IGRPMODR0_OFFSET]
385 str w4, [x5, #GICR_IPRIORITYR3_OFFSET]
389 str w3, [x5, #GICR_ISENABLER0_OFFSET]
415 str w1, [x5, #GICR_ICPENDR0_OFFSET]
423 str w0, [x3, #SYS_COUNTER_CNTCR_OFFSET]
499 str w1, [x4, #GICR_ICENABLER0_OFFSET]
537 str w0, [x2, #RSTCNTL_OFFSET]
541 str w0, [x2, #RSTCNTL_OFFSET]
570 str w1, [x2, x0]
573 str w1, [x2, x0]
576 str w1, [x2, x0]
581 str w1, [x0]
600 str x0, [x1, #CCN_HN_F_SNP_DMN_CTL_CLR_OFFSET]
614 str w1, [x3, #PMU_CLAINACTSETR_OFFSET]
622 str w1, [x3, #PMU_CLL2FLUSHSETR_OFFSET]
630 str w1, [x3, #PMU_CLSL2FLUSHCLRR_OFFSET]
633 str w1, [x3, #PMU_CLSINACTSETR_OFFSET]
659 str w1, [x3, x0]
726 str w0, [x2, #SYS_COUNTER_CNTCR_OFFSET]
816 str w0, [x2, #SYS_COUNTER_CNTCR_OFFSET]
913 str x7, [x1, #CCN_HN_F_SNP_DMN_CTL_CLR_OFFSET]
928 str w4, [x2, x3]
1002 str w7, [x1, x15]
1011 str w8, [x1, x16]
1018 str w9, [x1, x17]
1025 str w10, [x1, x18]
1046 str w11, [x1, x19]
1053 str w12, [x1, x20]
1158 str w7, [x3, #DCFG_DEVDISR1_OFFSET]
1161 str w8, [x3, #DCFG_DEVDISR2_OFFSET]
1164 str w9, [x3, #DCFG_DEVDISR3_OFFSET]
1167 str w10, [x3, #DCFG_DEVDISR4_OFFSET]
1170 str w11, [x3, #DCFG_DEVDISR5_OFFSET]
1173 str w12, [x3, #DCFG_DEVDISR6_OFFSET]
1228 str w18, [x3, #DCFG_DEVDISR6_OFFSET]
1229 str w17, [x3, #DCFG_DEVDISR5_OFFSET]
1230 str w16, [x3, #DCFG_DEVDISR4_OFFSET]
1231 str w15, [x3, #DCFG_DEVDISR3_OFFSET]
1232 str w14, [x3, #DCFG_DEVDISR2_OFFSET]
1233 str w13, [x3, #DCFG_DEVDISR1_OFFSET]
1243 str w14, [x1, x15]
1245 str w13, [x1, x16]
1247 str w12, [x1, x17]
1249 str w11, [x1, x18]
1251 str w10, [x1, x19]
1253 str w9, [x1, x20]
1320 str w9, [x2, x8]
1334 str x7, [x9, #CCN_HN_F_SNP_DMN_CTL_SET_OFFSET]
1400 str w8, [x4, #DDR_CFG_2_OFFSET]
1405 str w8, [x5, #DDR_CFG_2_OFFSET]
1411 str w9, [x1, x16]
1430 str w9, [x3, #DCFG_DEVDISR5_OFFSET]
1434 str w8, [x1, x12]
1438 str w9, [x1, x13]
1455 str w9, [x1, x15]
1459 str w8, [x1, x14]
1463 str w7, [x3, #DCFG_DEVDISR5_OFFSET]
1465 str w6, [x1, x16]
1486 str w9, [x5, #DDR_CFG_2_OFFSET]
1491 str w9, [x4, #DDR_CFG_2_OFFSET]
1631 str w1, [x0, #DCFG_COREDISR_OFFSET]
1635 str w2, [x0, #DCFG_COREDISABLEDSR_OFFSET]
1666 str w0, [x1]
1672 str w0, [x1]
1678 str w0, [x1]
1685 str w0, [x1]
1697 str w1, [x2, x0]
1802 str w1, [x2, x0]