Lines Matching refs:w1

200 	str	w1, [x2, #DCFG_BOOTLOCPTRL_OFFSET]
204 	str	w1, [x2, #DCFG_BOOTLOCPTRH_OFFSET]
256 	ldr	w1, [x1, #DCFG_COREDISABLEDSR_OFFSET]
259 	and	w0, w1, w0
425 	mvn	w1, wzr
426 	str	w1, [x5, #GICR_ICPENDR0_OFFSET]
510 	mov	w1, #GICR_ICENABLER0_SGI15
511 	str	w1, [x4, #GICR_ICENABLER0_OFFSET]
549 	mov	w1, wzr
555 	mov	w1, #RSTCR_RESET_REQ
588 	ldr	w1, [x0, #RST_RSTRQMR1_OFFSET]
589 	orr	w1, w1, #RSTRQMR_RPTOE_MASK
590 	str	w1, [x0, #RST_RSTRQMR1_OFFSET]
595 	ldr	w1, =DCFG_DEVDISR1_SEC
596 	str	w1, [x2, x0]
598 	ldr	w1, =DCFG_DEVDISR3_QBMAIN
599 	str	w1, [x2, x0]
601 	ldr	w1, =DCFG_DEVDISR4_SPI_QSPI
602 	str	w1, [x2, x0]
606 	mov	w1, #0x1
607 	str	w1, [x0]
625 	mov	w1, #0x1
626 	str	w1, [x0]
665 	ldr	w1, =PMU_POWMGTCSR_VAL
666 	str	w1, [x3, x0]
896 	ldr	w1, [x0, #PMU_PCPW20SR_OFFSET]
897 	cmp	w1, w3
1167 	ldr	w1, [x2, x0]
1168 	mov	w13, w1
1170 	str	w1, [x2, x0]
1173 	ldr	w1, [x2, x0]
1174 	mov	w14, w1
1176 	str	w1, [x2, x0]
1182 	ldr	w1, [x2, x0]
1183 	mov	w15, w1
1185 	str	w1, [x2, x0]
1189 	ldr	w1, [x2, x0]
1190 	mov	w16, w1
1193 	str	w1, [x2, x0]
1197 	ldr	w1, [x2, x0]
1198 	mov	w17, w1
1201 	str	w1, [x2, x0]
1205 	ldr	w1, [x2, x0]
1206 	mov	w18, w1
1208 	str	w1, [x2, x0]
1224 	ldr	w1, =RSTRQMR_RPTOE_MASK
1225 	str	w1, [x0, #RST_RSTRQMR1_OFFSET]
1230 	ldr	w1, =DCFG_DEVDISR1_SEC
1231 	str	w1, [x2, x0]
1233 	ldr	w1, =DCFG_DEVDISR3_QBMAIN
1234 	str	w1, [x2, x0]
1236 	ldr	w1, =DCFG_DEVDISR4_SPI_QSPI
1237 	str	w1, [x2, x0]
1251 	ldr	w1, [x0, #GICR_WAKER_OFFSET]
1252 	orr	w1, w1, #GICR_WAKER_SLEEP_BIT
1253 	str	w1, [x0, #GICR_WAKER_OFFSET]
1255 	ldr	w1, [x0, #GICR_WAKER_OFFSET]
1256 	cmp	w1, #GICR_WAKER_ASLEEP
1291 	ldr	w1, [x0, #GICR_WAKER_OFFSET]
1292 	bic	w1, w1, #GICR_WAKER_SLEEP_BIT
1293 	str	w1, [x0, #GICR_WAKER_OFFSET]
1295 	ldr	w1, [x0, #GICR_WAKER_OFFSET]
1296 	cbnz	w1, 1b
1377 	str	w1, [x3, #EPU_EPCCR10_OFFSET]
1467 	str	w1, [x2, x0]
1541 	clz	w1, w0
1543 	sub	w2, w2, w1
1567 	clz	w1, w0
1569 	sub	w2, w2, w1
1593 	mov	w1, #31
1594 	sub	w0, w1, w0
1598 	mov	w1, wzr
1603 	add	w1, w1, #MPIDR_CLUSTER
1608 	orr	w0, w1, w0
1619 	str	w1, [x2, x0]
1702 	ldr	w1, [x7, x11]
1703 	tst	w1, w3
1722 	ldr	w1, [x23, #EPU_EPCTR10_OFFSET]
1723 	cbz	w1, 5b
1736 	ldr	w1, [x7, x11]
1737 	tst	w1, w3
1765 	mov	w1, w17
1767 	str	w1, [x8, #DCFG_DEVDISR5_OFFSET]
1768 	mov	w1, w16
1770 	str	w1, [x8, #DCFG_DEVDISR4_OFFSET]
1771 	mov	w1, w15
1777 	str	w1, [x8, #DCFG_DEVDISR3_OFFSET]
1778 	mov	w1, w14
1780 	str	w1, [x8, #DCFG_DEVDISR2_OFFSET]
1781 	mov	w1, w13
1783 	str	w1, [x8, #DCFG_DEVDISR1_OFFSET]