Lines Matching refs:to

17 # set to GIC400 or GIC500
20 # set to CCI400 or CCN504 or CCN508
23 # indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
32 # Select the DDR PHY generation to be used
37 # ddr controller - set to MMDC or NXP
40 # ddr phy - set to NXP or SNPS
46 # Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def
47 # Input to CST create_hdr_esbc tool
68 # BL2_HDR_LOC has to be (OCRAM_START_ADDR + OCRAM_SIZE - NXP_ROM_RSVD - CSF_HDR_SZ)
70 # Input to CST create_hdr_isbc tool
72 # Covert to HEX to be used by create_pbl.mk
79 # SoC ERRATAS to be enabled