Lines Matching refs:w1

167 	ldr	w1, [x4, #GICD_CTLR_OFFSET]
168 	orr	w1, w1, #GICD_CTLR_EN_GRP0
169 	str	w1, [x4, #GICD_CTLR_OFFSET]
180 	lsl	w1, w3, #16
181 	orr	w1, w1, #0xF
182 	str	w1, [x4, #GICD_SGIR_OFFSET]
205 	ldr	w1, [x1, #DCFG_COREDISR_OFFSET]
206 	rev	w2, w1
223 	mov	w1, wzr
224 	str	w1, [x2, #DCFG_RSTRQMR1_OFFSET]
229 	ldr	w1, =RSTCR_RESET_REQ
231 	rev	w0, w1
550 	ldr	w1, [x6, #DDR_TIMING_CFG_4_OFFSET]
551 	rev	w2, w1
554 	rev	w1, w2
555 	str	w1, [x6, #DDR_TIMING_CFG_4_OFFSET]
737 	ldr	w1, [x2, #GICC_CTLR_OFFSET]
738 	bic	w1, w1, #GICC_CTLR_EN_GRP0
739 	str	w1, [x2, #GICC_CTLR_OFFSET]
758 	rev	w3, w1
763 	rev	w3, w1
1228 	ldr	w1, [x6, #DDR_TIMING_CFG_4_OFFSET]
1229 	rev	w2, w1
1232 	rev	w1, w2
1233 	str	w1, [x6, #DDR_TIMING_CFG_4_OFFSET]
1283 	rev	w3, w1
1294 	ldr	w1, [x2, x0]
1296 	rev	w0, w1
1308 	rev	w3, w1
1320 	ldr	w1, [x2, x0]
1322 	rev	w0, w1
1334 	rev	w3, w1
1346 	ldr	w1, [x2, x0]
1348 	rev	w0, w1
1360 	rev	w3, w1
1372 	ldr	w1, [x2, x0]
1374 	rev	w0, w1
1386 	ldr	w1, [x0, #DCFG_SVR_OFFSET]
1387 	rev	w0, w1
1403 	ldr	w1, [x0, #SCFG_GIC400_ADDR_ALIGN_OFFSET]
1404 	rev	w0, w1
1430 	ldr	w1, [x0, #DCFG_SVR_OFFSET]
1431 	rev	w0, w1
1447 	ldr	w1, [x0, #SCFG_GIC400_ADDR_ALIGN_OFFSET]
1448 	rev	w0, w1
1507 	ldr	w1, [x7, #RCPM2_IPSTPACKR4_OFFSET]
1508 	tst	w1, w3
1531 	ldr	w1, [x7, #RCPM2_IPSTPACKR4_OFFSET] /* poll on ipstpack4 - start */
1532 	tst	w1, w3
1547 	rev	w1, w17
1552 	str	w1, [x8, #DCFG_DEVDISR5_OFFSET]    /* reset devdisr5 */
1553 	rev	w1, w16
1554 	str	w1, [x8, #DCFG_DEVDISR4_OFFSET]    /* reset devdisr4 */
1555 	rev	w1, w15
1556 	str	w1, [x8, #DCFG_DEVDISR3_OFFSET]    /* reset devdisr3 */
1557 	rev	w1, w14
1558 	str	w1, [x8, #DCFG_DEVDISR2_OFFSET]    /* reset devdisr2 */
1559 	rev	w1, w13
1560 	str	w1, [x8, #DCFG_DEVDISR1_OFFSET]    /* reset devdisr1 */
1619 	ldr	w1, [x7, #RCPM2_IPSTPACKR4_OFFSET]
1620 	tst	w1, w3