Lines Matching refs:w1

138 	ldr	w1, [x1, #DCFG_COREDISABLEDSR_OFFSET]
141 	and	w0, w1, w0
211 	str	w1, [x2, #DCFG_BOOTLOCPTRL_OFFSET]
215 	str	w1, [x2, #DCFG_BOOTLOCPTRH_OFFSET]
382 	mvn	w1, wzr
383 	str	w1, [x5, #GICR_ICPENDR0_OFFSET]
467 	mov	w1, #GICR_ICENABLER0_SGI15
468 	str	w1, [x4, #GICR_ICENABLER0_OFFSET]
506 	mov	w1, wzr
512 	mov	w1, #RSTCR_RESET_REQ
549 	ldr	w1, =DCFG_DEVDISR1_SEC
550 	str	w1, [x2, x0]
552 	ldr	w1, =DCFG_DEVDISR4_SPI_QSPI
553 	str	w1, [x2, x0]
557 	mov	w1, #0x1
558 	str	w1, [x0]
577 	mov	w1, #0x1
578 	str	w1, [x0]
585 	ldr	w1, [x3, #PMU_PCPW20SR_OFFSET]
586 	cmp	w1, w0
596 	ldr	w1, [x3, #PMU_PCPW20SR_OFFSET]
597 	cmp	w1, w0
604 	ldr	w1, [x3, #PMU_CLL2FLUSHSR_OFFSET]
605 	cmp	w1, w0
635 	ldr	w1, =PMU_POWMGTCSR_VAL
636 	str	w1, [x3, x0]
942 	ldr	w1, =DCFG_DEVDISR1_SEC
943 	str	w1, [x2, x0]
946 	ldr	w1, =DCFG_DEVDISR4_SPI_QSPI
947 	str	w1, [x2, x0]
953 	mov	w1, #0x1
954 	str	w1, [x0]
958 	mov	w1, #0x1
959 	str	w1, [x0]
972 	ldr	w1, [x3, #PMU_PCPW20SR_OFFSET]
973 	cmp	w1, w0
988 	ldr	w1, [x3, #PMU_PCPW20SR_OFFSET]
989 	cmp	w1, w0
1000 	ldr	w1, [x3, #PMU_CLL2FLUSHSR_OFFSET]
1001 	cmp	w1, w0
1026 	ldr	w1, [x0, #GICR_WAKER_OFFSET]
1027 	orr	w1, w1, #GICR_WAKER_SLEEP_BIT
1028 	str	w1, [x0, #GICR_WAKER_OFFSET]
1030 	ldr	w1, [x0, #GICR_WAKER_OFFSET]
1031 	cmp	w1, #GICR_WAKER_ASLEEP
1045 	ldr	w1, =PMU_POWMGTCSR_VAL
1046 	str	w1, [x3, x0]
1051 	ldr	w1, [x5, #EPU_EPCTR10_OFFSET]
1052 	cmp	w1, #0
1066 	ldr	w1, [x3, #PMU_CLAINACTSETR_OFFSET]
1067 	cbnz	w1, 3b
1069 	ldr	w1, [x3, #PMU_CLSINACTSETR_OFFSET]
1070 	cbnz	w1, 4b
1083 	ldr	w1, [x0, #GICR_WAKER_OFFSET]
1084 	bic	w1, w1, #GICR_WAKER_SLEEP_BIT
1085 	str	w1, [x0, #GICR_WAKER_OFFSET]
1087 	ldr	w1, [x0, #GICR_WAKER_OFFSET]
1088 	cbnz	w1, 1b
1128 	str	w1, [x3, #EPU_EPCCR10_OFFSET]
1278 	str	w1, [x2, x0]
1289 	ldr	w1, [x2, x0]
1290 	mov	w0, w1
1302 	mov	w1, #31
1303 	sub	w0, w1, w0
1306 	mov	w1, wzr
1309 	orr	w1, w1, #1
1313 	orr	w0, w1, w0, lsl #8
1326 	clz	w1, w0
1328 	sub	w2, w2, w1
1351 	clz	w1, w0
1353 	sub	w2, w2, w1
1375 	str	w1, [x2, x0]