soc-ls1028a/aarch64/ls1028a.S

183 	str	w0, [x1, #CORE_HOLD_OFFSET]
189 	str	w2, [x1, #BRR_OFFSET]
211 	str	w1, [x2, #DCFG_BOOTLOCPTRL_OFFSET]
215 	str	w1, [x2, #DCFG_BOOTLOCPTRH_OFFSET]
236 	str	w2, [x5, #GICD_CTLR_OFFSET]
324 	str	w3, [x5, #GICR_ICENABLER0_OFFSET]
342 	str	w4, [x5, #GICR_IGROUPR0_OFFSET]
347 	str	w3, [x5, #GICR_IGRPMODR0_OFFSET]
352 	str	w4, [x5, #GICR_IPRIORITYR3_OFFSET]
356 	str	w3, [x5, #GICR_ISENABLER0_OFFSET]
383 	str	w1, [x5, #GICR_ICPENDR0_OFFSET]
391 	str	w0, [x3, #SYS_COUNTER_CNTCR_OFFSET]
468 	str	w1, [x4, #GICR_ICENABLER0_OFFSET]
550 	str	w1, [x2, x0]
553 	str	w1, [x2, x0]
558 	str	w1, [x0]
578 	str	w1, [x0]
591 	str	w0, [x3, #PMU_CLAINACTSETR_OFFSET]
602 	str	w0, [x3, #PMU_CLL2FLUSHSETR_OFFSET]
608 	str	w0, [x3, #PMU_CLSL2FLUSHCLRR_OFFSET]
610 	str	w0, [x3, #PMU_CLSINACTSETR_OFFSET]
636 	str	w1, [x3, x0]
701 	str	w0, [x2, #SYS_COUNTER_CNTCR_OFFSET]
785 	str	w0, [x2, #SYS_COUNTER_CNTCR_OFFSET]
895 	str	w4, [x2, #EPU_EPIMCR10_OFFSET]
896 	str	w5, [x2, #EPU_EPCCR10_OFFSET]
897 	str	w6, [x2, #EPU_EPCTR10_OFFSET]
898 	str	w7, [x2, #EPU_EPGCR_OFFSET]
928 	str	w4, [x2, x0]
929 	str	w4, [x2, x1]
932 	str	w4, [x2, x0]
933 	str	w4, [x2, x1]
943 	str	w1, [x2, x0]
947 	str	w1, [x2, x0]
954 	str	w1, [x0]
959 	str	w1, [x0]
982 	str	w0, [x3, #PMU_CLAINACTSETR_OFFSET]
996 	str	w0, [x3, #PMU_CLL2FLUSHSETR_OFFSET]
1006 	str	w0, [x3, #PMU_CLSL2FLUSHCLRR_OFFSET]
1008 	str	w0, [x3, #PMU_CLSINACTSETR_OFFSET]
1028 	str	w1, [x0, #GICR_WAKER_OFFSET]
1046 	str	w1, [x3, x0]
1061 	str	w0, [x3, #PMU_CLAINACTCLRR_OFFSET]
1062 	str	w0, [x3, #PMU_CLSINACTCLRR_OFFSET]
1085 	str	w1, [x0, #GICR_WAKER_OFFSET]
1095 	str	wzr, [x0]
1105 	str	wzr, [x2, #DCFG_DEVDISR1_OFFSET]
1106 	str	wzr, [x2, #DCFG_DEVDISR2_OFFSET]
1107 	str	wzr, [x2, #DCFG_DEVDISR4_OFFSET]
1113 	str	w2, [x3, x1]
1115 	str	w0, [x3, x1]
1118 	str	w2, [x3, x1]
1120 	str	w0, [x3, x1]
1125 	str	w2, [x3, #EPU_EPGCR_OFFSET]
1126 	str	w0, [x3, #EPU_EPCTR10_OFFSET]
1128 	str	w1, [x3, #EPU_EPCCR10_OFFSET]
1129 	str	w2, [x3, #EPU_EPIMCR10_OFFSET]
1173 	str	w0, [x1]
1177 	str	w0, [x1]
1181 	str	w0, [x1]
1186 	str	w0, [x1]
1201 	str	w0, [x1, #SECMON_HPCOMR_OFFSET]
1278 	str	w1, [x2, x0]
1375 	str	w1, [x2, x0]