165 	const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();  in plat_early_platform_setup()  local
174 	tegra_memctrl_tzdram_setup(plat_params->tzdram_base,  in plat_early_platform_setup()
175 			(uint32_t)plat_params->tzdram_size);  in plat_early_platform_setup()
178 	if (plat_params->l2_ecc_parity_prot_dis != 1) {  in plat_early_platform_setup()
204 	const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();  in plat_late_platform_setup()  local
210 	if (plat_params->sc7entry_fw_base && plat_params->sc7entry_fw_size) {  in plat_late_platform_setup()
212 		assert(plat_params->sc7entry_fw_size <= TEGRA_IRAM_A_SIZE);  in plat_late_platform_setup()
221 		assert(plat_params->tzdram_base > plat_params->sc7entry_fw_base);  in plat_late_platform_setup()
223 		sc7entry_end = plat_params->sc7entry_fw_base +  in plat_late_platform_setup()
224 			       plat_params->sc7entry_fw_size;  in plat_late_platform_setup()
225 		assert(sc7entry_end < plat_params->tzdram_base);  in plat_late_platform_setup()
228 		offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base;  in plat_late_platform_setup()
232 		tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base,  in plat_late_platform_setup()
233 			plat_params->tzdram_size + offset);  in plat_late_platform_setup()
239 		ret = mmap_add_dynamic_region(plat_params->sc7entry_fw_base,  in plat_late_platform_setup()
240 				plat_params->sc7entry_fw_base,  in plat_late_platform_setup()
241 				plat_params->sc7entry_fw_size,  in plat_late_platform_setup()
281 	const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();  in plat_supports_system_suspend()  local
286 	if (!tegra_chipid_is_t210_b01() && (plat_params->sc7entry_fw_base != 0U)) {  in plat_supports_system_suspend()