Lines Matching refs:MCUCFG_REG
33 #define MCUCFG_REG(ofs) (uint32_t)(MCUCFG_BASE + (ofs)) macro
68 #define SPM_MCUSYS_PWR_CON MCUCFG_REG(0xd200)
69 #define SPM_MP0_CPUTOP_PWR_CON MCUCFG_REG(0xd204)
70 #define SPM_MP0_CPU0_PWR_CON MCUCFG_REG(0xd208)
71 #define SPM_MP0_CPU1_PWR_CON MCUCFG_REG(0xd20c)
72 #define SPM_MP0_CPU2_PWR_CON MCUCFG_REG(0xd210)
73 #define SPM_MP0_CPU3_PWR_CON MCUCFG_REG(0xd214)
74 #define SPM_MP0_CPU4_PWR_CON MCUCFG_REG(0xd218)
75 #define SPM_MP0_CPU5_PWR_CON MCUCFG_REG(0xd21c)
76 #define SPM_MP0_CPU6_PWR_CON MCUCFG_REG(0xd220)
77 #define SPM_MP0_CPU7_PWR_CON MCUCFG_REG(0xd224)
100 #define MCUCFG_MP0_CLUSTER_CFG5 MCUCFG_REG(0xc8e4)
102 #define MCUCFG_MP0_CLUSTER_CFG8 MCUCFG_REG(0xc900)
103 #define MCUCFG_MP0_CLUSTER_CFG10 MCUCFG_REG(0xc908)
104 #define MCUCFG_MP0_CLUSTER_CFG12 MCUCFG_REG(0xc910)
105 #define MCUCFG_MP0_CLUSTER_CFG14 MCUCFG_REG(0xc918)
106 #define MCUCFG_MP0_CLUSTER_CFG16 MCUCFG_REG(0xc920)
107 #define MCUCFG_MP0_CLUSTER_CFG18 MCUCFG_REG(0xc928)
108 #define MCUCFG_MP0_CLUSTER_CFG20 MCUCFG_REG(0xc930)
109 #define MCUCFG_MP0_CLUSTER_CFG22 MCUCFG_REG(0xc938)
112 #define DREQ20_BIG_VPROC_ISO MCUCFG_REG(0xad8c)
126 #define MCUCFG_CPC_FLOW_CTRL_CFG MCUCFG_REG(0xa814)
127 #define MCUCFG_CPC_SPMC_PWR_STATUS MCUCFG_REG(0xa840)
158 #define PTP3_CPU0_SPMC_SW_CFG MCUCFG_REG(0x200)
159 #define CPU0_ILDO_CONTROL5 MCUCFG_REG(0x334)
160 #define CPU0_ILDO_CONTROL8 MCUCFG_REG(0x340)