Lines Matching refs:apupwr_writel
76 apupwr_writel(init_acc_cfg[i].val, in apupwr_smc_acc_init_all()
99 apupwr_writel(BIT(BIT_CGEN_APU), aacc_set[V_APU_CONN]); in apupwr_smc_acc_top()
100 apupwr_writel(BIT(BIT_CGEN_APU), aacc_set[V_TOP_IOMMU]); in apupwr_smc_acc_top()
102 apupwr_writel(BIT(BIT_CGEN_APU), aacc_clr[V_APU_CONN]); in apupwr_smc_acc_top()
103 apupwr_writel(BIT(BIT_CGEN_APU), aacc_clr[V_TOP_IOMMU]); in apupwr_smc_acc_top()
146 apupwr_writel(BIT(BIT_SEL_PARK), acc_set); in apupwr_smc_acc_set_parent()
147 apupwr_writel(BIT(BIT_SEL_F26M), acc_clr); in apupwr_smc_acc_set_parent()
149 apupwr_writel(BIT(BIT_CGEN_PARK), acc_set); in apupwr_smc_acc_set_parent()
150 apupwr_writel(BIT(BIT_CGEN_F26M) | BIT(BIT_CGEN_SOC), acc_clr); in apupwr_smc_acc_set_parent()
152 apupwr_writel(BIT(BIT_SEL_APU), acc_clr); in apupwr_smc_acc_set_parent()
154 apupwr_writel(BIT(BIT_SEL_APU_DIV2), acc_clr); in apupwr_smc_acc_set_parent()
159 apupwr_writel(BIT(BIT_SEL_APU), acc_set); in apupwr_smc_acc_set_parent()
161 apupwr_writel(BIT(BIT_CGEN_PARK) | BIT(BIT_CGEN_F26M) | in apupwr_smc_acc_set_parent()
167 apupwr_writel(BIT(BIT_SEL_PARK), acc_clr); in apupwr_smc_acc_set_parent()
168 apupwr_writel(BIT(BIT_SEL_F26M), acc_clr); in apupwr_smc_acc_set_parent()
170 apupwr_writel(BIT(BIT_CGEN_SOC), acc_set); in apupwr_smc_acc_set_parent()
171 apupwr_writel(BIT(BIT_CGEN_F26M) | BIT(BIT_CGEN_PARK), acc_clr); in apupwr_smc_acc_set_parent()
173 apupwr_writel(BIT(BIT_SEL_APU), acc_clr); in apupwr_smc_acc_set_parent()
175 apupwr_writel(BIT(BIT_SEL_APU_DIV2), acc_clr); in apupwr_smc_acc_set_parent()
182 apupwr_writel(BIT(BIT_SEL_F26M), acc_set); in apupwr_smc_acc_set_parent()
183 apupwr_writel(BIT(BIT_SEL_PARK), acc_clr); in apupwr_smc_acc_set_parent()
185 apupwr_writel(BIT(BIT_CGEN_F26M), acc_set); in apupwr_smc_acc_set_parent()
186 apupwr_writel(BIT(BIT_CGEN_PARK) | BIT(BIT_CGEN_SOC), acc_clr); in apupwr_smc_acc_set_parent()
188 apupwr_writel(BIT(BIT_SEL_APU), acc_clr); in apupwr_smc_acc_set_parent()
190 apupwr_writel(BIT(BIT_SEL_APU_DIV2), acc_clr); in apupwr_smc_acc_set_parent()
254 apupwr_writel(BIT(BIT_SEL_APU_DIV2), acc_set0); in apupwr_smc_pll_set_rate()
256 apupwr_writel(BIT(BIT_SEL_APU_DIV2), acc_set1); in apupwr_smc_pll_set_rate()