19 static unsigned long cci_base_addr;  variable
30 	cci_base_addr = cci_base;  in mcsi_init()
43 	mmio_write_32(cci_base_addr + FLUSH_SF, 0x1);  in mcsi_cache_flush()
46 		if ((mmio_read_32(cci_base_addr + FLUSH_SF) & 0x1) == 0x0)  in mcsi_cache_flush()
73 	return cci_base_addr + cci_cluster_ix_to_iface[cluster_id];  in get_slave_iface_base()
83 	assert(cci_base_addr);  in cci_enable_cluster_coherency()
88 		   cci_base_addr + SNP_PENDING_REG)) >> SNP_PENDING;  in cci_enable_cluster_coherency()
91 			   cci_base_addr + SNP_PENDING_REG)) >> SNP_PENDING;  in cci_enable_cluster_coherency()
102 	while (mmio_read_32(cci_base_addr + SNP_PENDING_REG) >> SNP_PENDING)  in cci_enable_cluster_coherency()
115 	assert(cci_base_addr);  in cci_disable_cluster_coherency()
118 	while (mmio_read_32(cci_base_addr + SNP_PENDING_REG) >> SNP_PENDING)  in cci_disable_cluster_coherency()
132 	while (mmio_read_32(cci_base_addr + SNP_PENDING_REG) >> SNP_PENDING)  in cci_disable_cluster_coherency()
140 	config = mmio_read_32(cci_base_addr + CENTRAL_CTRL_REG);  in cci_secure_switch()
145 	mmio_write_32(cci_base_addr + CENTRAL_CTRL_REG, config);  in cci_secure_switch()
152 	config = mmio_read_32(cci_base_addr + CENTRAL_CTRL_REG);  in cci_pmu_secure_switch()
157 	mmio_write_32(cci_base_addr + CENTRAL_CTRL_REG, config);  in cci_pmu_secure_switch()
162 	while (mmio_read_32(cci_base_addr + SNP_PENDING_REG) >> SNP_PENDING)  in cci_init_sf()
165 	mmio_write_32(cci_base_addr + SF_INIT_REG, TRIG_SF1_INIT);  in cci_init_sf()
166 	while (mmio_read_32(cci_base_addr + SF_INIT_REG) & TRIG_SF1_INIT)  in cci_init_sf()
168 	while (!(mmio_read_32(cci_base_addr + SF_INIT_REG) & SF1_INIT_DONE))  in cci_init_sf()
171 	mmio_write_32(cci_base_addr + SF_INIT_REG, TRIG_SF2_INIT);  in cci_init_sf()
172 	while (mmio_read_32(cci_base_addr + SF_INIT_REG) & TRIG_SF2_INIT)  in cci_init_sf()
174 	while (!(mmio_read_32(cci_base_addr + SF_INIT_REG) & SF2_INIT_DONE))  in cci_init_sf()
180 	mmio_setbits_32(cci_base_addr + CENTRAL_CTRL_REG, INT_EN);  in cci_interrupt_en()
188 	if ((cci_base_addr == 0) || (offset > MSCI_MEMORY_SZ))  in cci_reg_access()
193 		ret = mmio_read_32(cci_base_addr + offset);  in cci_reg_access()
196 		mmio_write_32(cci_base_addr + offset, val);  in cci_reg_access()
200 		mmio_setbits_32(cci_base_addr + offset, val);  in cci_reg_access()
204 		mmio_clrbits_32(cci_base_addr + offset, val);  in cci_reg_access()