Lines Matching defs:mt8173_mcucfg_regs

13 struct mt8173_mcucfg_regs {  struct
14 	uint32_t mp0_ca7l_cache_config;
15 	struct {
18 	} mp0_cpu[4];
19 	uint32_t mp0_cache_mem_delsel0;
20 	uint32_t mp0_cache_mem_delsel1;
21 	uint32_t mp0_axi_config;
22 	uint32_t mp0_misc_config[2];
23 	struct {
26 	} mp0_rv_addr[4];
27 	uint32_t mp0_ca7l_cfg_dis;
28 	uint32_t mp0_ca7l_clken_ctrl;
29 	uint32_t mp0_ca7l_rst_ctrl;
30 	uint32_t mp0_ca7l_misc_config;
31 	uint32_t mp0_ca7l_dbg_pwr_ctrl;
32 	uint32_t mp0_rw_rsvd0;
33 	uint32_t mp0_rw_rsvd1;
34 	uint32_t mp0_ro_rsvd;
35 	uint32_t reserved0_0[100];
36 	uint32_t mp1_cpucfg;
37 	uint32_t mp1_miscdbg;
38 	uint32_t reserved0_1[13];
39 	uint32_t mp1_rst_ctl;
40 	uint32_t mp1_clkenm_div;
41 	uint32_t reserved0_2[7];
42 	uint32_t mp1_config_res;
43 	uint32_t reserved0_3[13];
44 	struct {
47 	} mp1_rv_addr[2];
48 	uint32_t reserved0_4[84];
49 	uint32_t mp0_rst_status;		/* 0x400 */
50 	uint32_t mp0_dbg_ctrl;
51 	uint32_t mp0_dbg_flag;
52 	uint32_t mp0_ca7l_ir_mon;
53 	struct {
62 	} mp0_dbg_core[4];
63 	uint32_t dfd_ctrl;
64 	uint32_t dfd_cnt_l;
65 	uint32_t dfd_cnt_h;
66 	uint32_t misccfg_mp0_rw_rsvd;
67 	uint32_t misccfg_sec_vio_status0;
68 	uint32_t misccfg_sec_vio_status1;
69 	uint32_t reserved1[22];
70 	uint32_t misccfg_rw_rsvd;		/* 0x500 */
71 	uint32_t mcusys_dbg_mon_sel_a;
72 	uint32_t mcusys_dbg_mon;
73 	uint32_t reserved2[61];
74 	uint32_t mcusys_config_a;		/* 0x600 */
75 	uint32_t mcusys_config1_a;
76 	uint32_t mcusys_gic_peribase_a;
77 	uint32_t reserved3;
78 	uint32_t sec_range0_start;		/* 0x610 */
79 	uint32_t sec_range0_end;
80 	uint32_t sec_range_enable;
104 static struct mt8173_mcucfg_regs *const mt8173_mcucfg = (void *)MCUCFG_BASE;  argument