Lines Matching refs:pwrctrl
65 void __spm_set_power_control(const struct pwr_ctrl *pwrctrl, in __spm_set_power_control() argument
70 ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 0) | in __spm_set_power_control()
71 (((pwrctrl->reg_spm_apsrc_req | in __spm_set_power_control()
73 (((pwrctrl->reg_spm_ddren_req | in __spm_set_power_control()
75 ((pwrctrl->reg_spm_dvfs_req & 0x1) << 3) | in __spm_set_power_control()
76 (((pwrctrl->reg_spm_emi_req | in __spm_set_power_control()
78 (((pwrctrl->reg_spm_f26m_req | in __spm_set_power_control()
81 (((pwrctrl->reg_spm_infra_req | in __spm_set_power_control()
83 (((pwrctrl->reg_spm_pmic_req | in __spm_set_power_control()
85 (((u32)pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 8) | in __spm_set_power_control()
86 (((u32)pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 9) | in __spm_set_power_control()
87 (((u32)pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 10) | in __spm_set_power_control()
88 ((((u32)pwrctrl->reg_spm_vcore_req | in __spm_set_power_control()
90 ((((u32)pwrctrl->reg_spm_vrf18_req | in __spm_set_power_control()
92 (((u32)pwrctrl->adsp_mailbox_state & 0x1) << 16) | in __spm_set_power_control()
93 (((u32)pwrctrl->apsrc_state & 0x1) << 17) | in __spm_set_power_control()
94 (((u32)pwrctrl->ddren_state & 0x1) << 18) | in __spm_set_power_control()
95 (((u32)pwrctrl->dvfs_state & 0x1) << 19) | in __spm_set_power_control()
96 (((u32)pwrctrl->emi_state & 0x1) << 20) | in __spm_set_power_control()
97 (((u32)pwrctrl->f26m_state & 0x1) << 21) | in __spm_set_power_control()
98 (((u32)pwrctrl->infra_state & 0x1) << 22) | in __spm_set_power_control()
99 (((u32)pwrctrl->pmic_state & 0x1) << 23) | in __spm_set_power_control()
100 (((u32)pwrctrl->scp_mailbox_state & 0x1) << 24) | in __spm_set_power_control()
101 (((u32)pwrctrl->sspm_mailbox_state & 0x1) << 25) | in __spm_set_power_control()
102 (((u32)pwrctrl->sw_mailbox_state & 0x1) << 26) | in __spm_set_power_control()
103 (((u32)pwrctrl->vcore_state & 0x1) << 27) | in __spm_set_power_control()
104 (((u32)pwrctrl->vrf18_state & 0x1) << 28)); in __spm_set_power_control()
108 (((u32)pwrctrl->reg_apifr_apsrc_rmb & 0x1) << 0) | in __spm_set_power_control()
109 (((u32)pwrctrl->reg_apifr_ddren_rmb & 0x1) << 1) | in __spm_set_power_control()
110 (((u32)pwrctrl->reg_apifr_emi_rmb & 0x1) << 2) | in __spm_set_power_control()
111 (((u32)pwrctrl->reg_apifr_infra_rmb & 0x1) << 3) | in __spm_set_power_control()
112 (((u32)pwrctrl->reg_apifr_pmic_rmb & 0x1) << 4) | in __spm_set_power_control()
113 (((u32)pwrctrl->reg_apifr_srcclkena_mb & 0x1) << 5) | in __spm_set_power_control()
114 (((u32)pwrctrl->reg_apifr_vcore_rmb & 0x1) << 6) | in __spm_set_power_control()
115 (((u32)pwrctrl->reg_apifr_vrf18_rmb & 0x1) << 7) | in __spm_set_power_control()
116 (((u32)pwrctrl->reg_apu_apsrc_rmb & 0x1) << 8) | in __spm_set_power_control()
117 (((u32)pwrctrl->reg_apu_ddren_rmb & 0x1) << 9) | in __spm_set_power_control()
118 (((u32)pwrctrl->reg_apu_emi_rmb & 0x1) << 10) | in __spm_set_power_control()
119 (((u32)pwrctrl->reg_apu_infra_rmb & 0x1) << 11) | in __spm_set_power_control()
120 (((u32)pwrctrl->reg_apu_pmic_rmb & 0x1) << 12) | in __spm_set_power_control()
121 (((u32)pwrctrl->reg_apu_srcclkena_mb & 0x1) << 13) | in __spm_set_power_control()
122 (((u32)pwrctrl->reg_apu_vcore_rmb & 0x1) << 14) | in __spm_set_power_control()
123 (((u32)pwrctrl->reg_apu_vrf18_rmb & 0x1) << 15) | in __spm_set_power_control()
124 (((u32)pwrctrl->reg_audio_apsrc_rmb & 0x1) << 16) | in __spm_set_power_control()
125 (((u32)pwrctrl->reg_audio_ddren_rmb & 0x1) << 17) | in __spm_set_power_control()
126 (((u32)pwrctrl->reg_audio_emi_rmb & 0x1) << 18) | in __spm_set_power_control()
127 (((u32)pwrctrl->reg_audio_infra_rmb & 0x1) << 19) | in __spm_set_power_control()
128 (((u32)pwrctrl->reg_audio_pmic_rmb & 0x1) << 20) | in __spm_set_power_control()
129 (((u32)pwrctrl->reg_audio_srcclkena_mb & 0x1) << 21) | in __spm_set_power_control()
130 (((u32)pwrctrl->reg_audio_vcore_rmb & 0x1) << 22) | in __spm_set_power_control()
131 (((u32)pwrctrl->reg_audio_vrf18_rmb & 0x1) << 23)); in __spm_set_power_control()
135 (((u32)pwrctrl->reg_audio_dsp_apsrc_rmb & 0x1) << 0) | in __spm_set_power_control()
136 (((u32)pwrctrl->reg_audio_dsp_ddren_rmb & 0x1) << 1) | in __spm_set_power_control()
137 (((u32)pwrctrl->reg_audio_dsp_emi_rmb & 0x1) << 2) | in __spm_set_power_control()
138 (((u32)pwrctrl->reg_audio_dsp_infra_rmb & 0x1) << 3) | in __spm_set_power_control()
139 (((u32)pwrctrl->reg_audio_dsp_pmic_rmb & 0x1) << 4) | in __spm_set_power_control()
140 (((u32)pwrctrl->reg_audio_dsp_srcclkena_mb & 0x1) << 5) | in __spm_set_power_control()
141 (((u32)pwrctrl->reg_audio_dsp_vcore_rmb & 0x1) << 6) | in __spm_set_power_control()
142 (((u32)pwrctrl->reg_audio_dsp_vrf18_rmb & 0x1) << 7) | in __spm_set_power_control()
143 (((u32)pwrctrl->reg_cam_apsrc_rmb & 0x1) << 8) | in __spm_set_power_control()
144 (((u32)pwrctrl->reg_cam_ddren_rmb & 0x1) << 9) | in __spm_set_power_control()
145 (((u32)pwrctrl->reg_cam_emi_rmb & 0x1) << 10) | in __spm_set_power_control()
146 (((u32)pwrctrl->reg_cam_infra_rmb & 0x1) << 11) | in __spm_set_power_control()
147 (((u32)pwrctrl->reg_cam_pmic_rmb & 0x1) << 12) | in __spm_set_power_control()
148 (((u32)pwrctrl->reg_cam_srcclkena_mb & 0x1) << 13) | in __spm_set_power_control()
149 (((u32)pwrctrl->reg_cam_vrf18_rmb & 0x1) << 14) | in __spm_set_power_control()
150 (((u32)pwrctrl->reg_ccif_apsrc_rmb & 0xfff) << 15)); in __spm_set_power_control()
154 (((u32)pwrctrl->reg_ccif_emi_rmb & 0xfff) << 0) | in __spm_set_power_control()
155 (((u32)pwrctrl->reg_ccif_infra_rmb & 0xfff) << 12)); in __spm_set_power_control()
159 (((u32)pwrctrl->reg_ccif_pmic_rmb & 0xfff) << 0) | in __spm_set_power_control()
160 (((u32)pwrctrl->reg_ccif_srcclkena_mb & 0xfff) << 12)); in __spm_set_power_control()
164 (((u32)pwrctrl->reg_ccif_vcore_rmb & 0xfff) << 0) | in __spm_set_power_control()
165 (((u32)pwrctrl->reg_ccif_vrf18_rmb & 0xfff) << 12) | in __spm_set_power_control()
166 (((u32)pwrctrl->reg_ccu_apsrc_rmb & 0x1) << 24) | in __spm_set_power_control()
167 (((u32)pwrctrl->reg_ccu_ddren_rmb & 0x1) << 25) | in __spm_set_power_control()
168 (((u32)pwrctrl->reg_ccu_emi_rmb & 0x1) << 26) | in __spm_set_power_control()
169 (((u32)pwrctrl->reg_ccu_infra_rmb & 0x1) << 27) | in __spm_set_power_control()
170 (((u32)pwrctrl->reg_ccu_pmic_rmb & 0x1) << 28) | in __spm_set_power_control()
171 (((u32)pwrctrl->reg_ccu_srcclkena_mb & 0x1) << 29) | in __spm_set_power_control()
172 (((u32)pwrctrl->reg_ccu_vrf18_rmb & 0x1) << 30) | in __spm_set_power_control()
173 (((u32)pwrctrl->reg_cg_check_apsrc_rmb & 0x1) << 31)); in __spm_set_power_control()
177 (((u32)pwrctrl->reg_cg_check_ddren_rmb & 0x1) << 0) | in __spm_set_power_control()
178 (((u32)pwrctrl->reg_cg_check_emi_rmb & 0x1) << 1) | in __spm_set_power_control()
179 (((u32)pwrctrl->reg_cg_check_infra_rmb & 0x1) << 2) | in __spm_set_power_control()
180 (((u32)pwrctrl->reg_cg_check_pmic_rmb & 0x1) << 3) | in __spm_set_power_control()
181 (((u32)pwrctrl->reg_cg_check_srcclkena_mb & 0x1) << 4) | in __spm_set_power_control()
182 (((u32)pwrctrl->reg_cg_check_vcore_rmb & 0x1) << 5) | in __spm_set_power_control()
183 (((u32)pwrctrl->reg_cg_check_vrf18_rmb & 0x1) << 6) | in __spm_set_power_control()
184 (((u32)pwrctrl->reg_cksys_apsrc_rmb & 0x1) << 7) | in __spm_set_power_control()
185 (((u32)pwrctrl->reg_cksys_ddren_rmb & 0x1) << 8) | in __spm_set_power_control()
186 (((u32)pwrctrl->reg_cksys_emi_rmb & 0x1) << 9) | in __spm_set_power_control()
187 (((u32)pwrctrl->reg_cksys_infra_rmb & 0x1) << 10) | in __spm_set_power_control()
188 (((u32)pwrctrl->reg_cksys_pmic_rmb & 0x1) << 11) | in __spm_set_power_control()
189 (((u32)pwrctrl->reg_cksys_srcclkena_mb & 0x1) << 12) | in __spm_set_power_control()
190 (((u32)pwrctrl->reg_cksys_vcore_rmb & 0x1) << 13) | in __spm_set_power_control()
191 (((u32)pwrctrl->reg_cksys_vrf18_rmb & 0x1) << 14) | in __spm_set_power_control()
192 (((u32)pwrctrl->reg_cksys_1_apsrc_rmb & 0x1) << 15) | in __spm_set_power_control()
193 (((u32)pwrctrl->reg_cksys_1_ddren_rmb & 0x1) << 16) | in __spm_set_power_control()
194 (((u32)pwrctrl->reg_cksys_1_emi_rmb & 0x1) << 17) | in __spm_set_power_control()
195 (((u32)pwrctrl->reg_cksys_1_infra_rmb & 0x1) << 18) | in __spm_set_power_control()
196 (((u32)pwrctrl->reg_cksys_1_pmic_rmb & 0x1) << 19) | in __spm_set_power_control()
197 (((u32)pwrctrl->reg_cksys_1_srcclkena_mb & 0x1) << 20) | in __spm_set_power_control()
198 (((u32)pwrctrl->reg_cksys_1_vcore_rmb & 0x1) << 21) | in __spm_set_power_control()
199 (((u32)pwrctrl->reg_cksys_1_vrf18_rmb & 0x1) << 22)); in __spm_set_power_control()
203 (((u32)pwrctrl->reg_cksys_2_apsrc_rmb & 0x1) << 0) | in __spm_set_power_control()
204 (((u32)pwrctrl->reg_cksys_2_ddren_rmb & 0x1) << 1) | in __spm_set_power_control()
205 (((u32)pwrctrl->reg_cksys_2_emi_rmb & 0x1) << 2) | in __spm_set_power_control()
206 (((u32)pwrctrl->reg_cksys_2_infra_rmb & 0x1) << 3) | in __spm_set_power_control()
207 (((u32)pwrctrl->reg_cksys_2_pmic_rmb & 0x1) << 4) | in __spm_set_power_control()
208 (((u32)pwrctrl->reg_cksys_2_srcclkena_mb & 0x1) << 5) | in __spm_set_power_control()
209 (((u32)pwrctrl->reg_cksys_2_vcore_rmb & 0x1) << 6) | in __spm_set_power_control()
210 (((u32)pwrctrl->reg_cksys_2_vrf18_rmb & 0x1) << 7) | in __spm_set_power_control()
211 (((u32)pwrctrl->reg_conn_apsrc_rmb & 0x1) << 8) | in __spm_set_power_control()
212 (((u32)pwrctrl->reg_conn_ddren_rmb & 0x1) << 9) | in __spm_set_power_control()
213 (((u32)pwrctrl->reg_conn_emi_rmb & 0x1) << 10) | in __spm_set_power_control()
214 (((u32)pwrctrl->reg_conn_infra_rmb & 0x1) << 11) | in __spm_set_power_control()
215 (((u32)pwrctrl->reg_conn_pmic_rmb & 0x1) << 12) | in __spm_set_power_control()
216 (((u32)pwrctrl->reg_conn_srcclkena_mb & 0x1) << 13) | in __spm_set_power_control()
217 (((u32)pwrctrl->reg_conn_srcclkenb_mb & 0x1) << 14) | in __spm_set_power_control()
218 (((u32)pwrctrl->reg_conn_vcore_rmb & 0x1) << 15) | in __spm_set_power_control()
219 (((u32)pwrctrl->reg_conn_vrf18_rmb & 0x1) << 16) | in __spm_set_power_control()
220 (((u32)pwrctrl->reg_corecfg_apsrc_rmb & 0x1) << 17) | in __spm_set_power_control()
221 (((u32)pwrctrl->reg_corecfg_ddren_rmb & 0x1) << 18) | in __spm_set_power_control()
222 (((u32)pwrctrl->reg_corecfg_emi_rmb & 0x1) << 19) | in __spm_set_power_control()
223 (((u32)pwrctrl->reg_corecfg_infra_rmb & 0x1) << 20) | in __spm_set_power_control()
224 (((u32)pwrctrl->reg_corecfg_pmic_rmb & 0x1) << 21) | in __spm_set_power_control()
225 (((u32)pwrctrl->reg_corecfg_srcclkena_mb & 0x1) << 22) | in __spm_set_power_control()
226 (((u32)pwrctrl->reg_corecfg_vcore_rmb & 0x1) << 23) | in __spm_set_power_control()
227 (((u32)pwrctrl->reg_corecfg_vrf18_rmb & 0x1) << 24)); in __spm_set_power_control()
231 (((u32)pwrctrl->reg_cpueb_apsrc_rmb & 0x1) << 0) | in __spm_set_power_control()
232 (((u32)pwrctrl->reg_cpueb_ddren_rmb & 0x1) << 1) | in __spm_set_power_control()
233 (((u32)pwrctrl->reg_cpueb_emi_rmb & 0x1) << 2) | in __spm_set_power_control()
234 (((u32)pwrctrl->reg_cpueb_infra_rmb & 0x1) << 3) | in __spm_set_power_control()
235 (((u32)pwrctrl->reg_cpueb_pmic_rmb & 0x1) << 4) | in __spm_set_power_control()
236 (((u32)pwrctrl->reg_cpueb_srcclkena_mb & 0x1) << 5) | in __spm_set_power_control()
237 (((u32)pwrctrl->reg_cpueb_vcore_rmb & 0x1) << 6) | in __spm_set_power_control()
238 (((u32)pwrctrl->reg_cpueb_vrf18_rmb & 0x1) << 7) | in __spm_set_power_control()
239 (((u32)pwrctrl->reg_disp0_apsrc_rmb & 0x1) << 8) | in __spm_set_power_control()
240 (((u32)pwrctrl->reg_disp0_ddren_rmb & 0x1) << 9) | in __spm_set_power_control()
241 (((u32)pwrctrl->reg_disp0_emi_rmb & 0x1) << 10) | in __spm_set_power_control()
242 (((u32)pwrctrl->reg_disp0_infra_rmb & 0x1) << 11) | in __spm_set_power_control()
243 (((u32)pwrctrl->reg_disp0_pmic_rmb & 0x1) << 12) | in __spm_set_power_control()
244 (((u32)pwrctrl->reg_disp0_srcclkena_mb & 0x1) << 13) | in __spm_set_power_control()
245 (((u32)pwrctrl->reg_disp0_vrf18_rmb & 0x1) << 14) | in __spm_set_power_control()
246 (((u32)pwrctrl->reg_disp1_apsrc_rmb & 0x1) << 15) | in __spm_set_power_control()
247 (((u32)pwrctrl->reg_disp1_ddren_rmb & 0x1) << 16) | in __spm_set_power_control()
248 (((u32)pwrctrl->reg_disp1_emi_rmb & 0x1) << 17) | in __spm_set_power_control()
249 (((u32)pwrctrl->reg_disp1_infra_rmb & 0x1) << 18) | in __spm_set_power_control()
250 (((u32)pwrctrl->reg_disp1_pmic_rmb & 0x1) << 19) | in __spm_set_power_control()
251 (((u32)pwrctrl->reg_disp1_srcclkena_mb & 0x1) << 20) | in __spm_set_power_control()
252 (((u32)pwrctrl->reg_disp1_vrf18_rmb & 0x1) << 21) | in __spm_set_power_control()
253 (((u32)pwrctrl->reg_dpm_apsrc_rmb & 0xf) << 22) | in __spm_set_power_control()
254 (((u32)pwrctrl->reg_dpm_ddren_rmb & 0xf) << 26)); in __spm_set_power_control()
258 (((u32)pwrctrl->reg_dpm_emi_rmb & 0xf) << 0) | in __spm_set_power_control()
259 (((u32)pwrctrl->reg_dpm_infra_rmb & 0xf) << 4) | in __spm_set_power_control()
260 (((u32)pwrctrl->reg_dpm_pmic_rmb & 0xf) << 8) | in __spm_set_power_control()
261 (((u32)pwrctrl->reg_dpm_srcclkena_mb & 0xf) << 12) | in __spm_set_power_control()
262 (((u32)pwrctrl->reg_dpm_vcore_rmb & 0xf) << 16) | in __spm_set_power_control()
263 (((u32)pwrctrl->reg_dpm_vrf18_rmb & 0xf) << 20) | in __spm_set_power_control()
264 (((u32)pwrctrl->reg_dpmaif_apsrc_rmb & 0x1) << 24) | in __spm_set_power_control()
265 (((u32)pwrctrl->reg_dpmaif_ddren_rmb & 0x1) << 25) | in __spm_set_power_control()
266 (((u32)pwrctrl->reg_dpmaif_emi_rmb & 0x1) << 26) | in __spm_set_power_control()
267 (((u32)pwrctrl->reg_dpmaif_infra_rmb & 0x1) << 27) | in __spm_set_power_control()
268 (((u32)pwrctrl->reg_dpmaif_pmic_rmb & 0x1) << 28) | in __spm_set_power_control()
269 (((u32)pwrctrl->reg_dpmaif_srcclkena_mb & 0x1) << 29) | in __spm_set_power_control()
270 (((u32)pwrctrl->reg_dpmaif_vcore_rmb & 0x1) << 30) | in __spm_set_power_control()
271 (((u32)pwrctrl->reg_dpmaif_vrf18_rmb & 0x1) << 31)); in __spm_set_power_control()
275 (((u32)pwrctrl->reg_dvfsrc_level_rmb & 0x1) << 0) | in __spm_set_power_control()
276 (((u32)pwrctrl->reg_emisys_apsrc_rmb & 0x1) << 1) | in __spm_set_power_control()
277 (((u32)pwrctrl->reg_emisys_ddren_rmb & 0x1) << 2) | in __spm_set_power_control()
278 (((u32)pwrctrl->reg_emisys_emi_rmb & 0x1) << 3) | in __spm_set_power_control()
279 (((u32)pwrctrl->reg_emisys_infra_rmb & 0x1) << 4) | in __spm_set_power_control()
280 (((u32)pwrctrl->reg_emisys_pmic_rmb & 0x1) << 5) | in __spm_set_power_control()
281 (((u32)pwrctrl->reg_emisys_srcclkena_mb & 0x1) << 6) | in __spm_set_power_control()
282 (((u32)pwrctrl->reg_emisys_vcore_rmb & 0x1) << 7) | in __spm_set_power_control()
283 (((u32)pwrctrl->reg_emisys_vrf18_rmb & 0x1) << 8) | in __spm_set_power_control()
284 (((u32)pwrctrl->reg_gce_apsrc_rmb & 0x1) << 9) | in __spm_set_power_control()
285 (((u32)pwrctrl->reg_gce_ddren_rmb & 0x1) << 10) | in __spm_set_power_control()
286 (((u32)pwrctrl->reg_gce_emi_rmb & 0x1) << 11) | in __spm_set_power_control()
287 (((u32)pwrctrl->reg_gce_infra_rmb & 0x1) << 12) | in __spm_set_power_control()
288 (((u32)pwrctrl->reg_gce_pmic_rmb & 0x1) << 13) | in __spm_set_power_control()
289 (((u32)pwrctrl->reg_gce_srcclkena_mb & 0x1) << 14) | in __spm_set_power_control()
290 (((u32)pwrctrl->reg_gce_vcore_rmb & 0x1) << 15) | in __spm_set_power_control()
291 (((u32)pwrctrl->reg_gce_vrf18_rmb & 0x1) << 16) | in __spm_set_power_control()
292 (((u32)pwrctrl->reg_gpueb_apsrc_rmb & 0x1) << 17) | in __spm_set_power_control()
293 (((u32)pwrctrl->reg_gpueb_ddren_rmb & 0x1) << 18) | in __spm_set_power_control()
294 (((u32)pwrctrl->reg_gpueb_emi_rmb & 0x1) << 19) | in __spm_set_power_control()
295 (((u32)pwrctrl->reg_gpueb_infra_rmb & 0x1) << 20) | in __spm_set_power_control()
296 (((u32)pwrctrl->reg_gpueb_pmic_rmb & 0x1) << 21) | in __spm_set_power_control()
297 (((u32)pwrctrl->reg_gpueb_srcclkena_mb & 0x1) << 22) | in __spm_set_power_control()
298 (((u32)pwrctrl->reg_gpueb_vcore_rmb & 0x1) << 23) | in __spm_set_power_control()
299 (((u32)pwrctrl->reg_gpueb_vrf18_rmb & 0x1) << 24) | in __spm_set_power_control()
300 (((u32)pwrctrl->reg_hwccf_apsrc_rmb & 0x1) << 25) | in __spm_set_power_control()
301 (((u32)pwrctrl->reg_hwccf_ddren_rmb & 0x1) << 26) | in __spm_set_power_control()
302 (((u32)pwrctrl->reg_hwccf_emi_rmb & 0x1) << 27) | in __spm_set_power_control()
303 (((u32)pwrctrl->reg_hwccf_infra_rmb & 0x1) << 28) | in __spm_set_power_control()
304 (((u32)pwrctrl->reg_hwccf_pmic_rmb & 0x1) << 29) | in __spm_set_power_control()
305 (((u32)pwrctrl->reg_hwccf_srcclkena_mb & 0x1) << 30) | in __spm_set_power_control()
306 (((u32)pwrctrl->reg_hwccf_vcore_rmb & 0x1) << 31)); in __spm_set_power_control()
310 (((u32)pwrctrl->reg_hwccf_vrf18_rmb & 0x1) << 0) | in __spm_set_power_control()
311 (((u32)pwrctrl->reg_img_apsrc_rmb & 0x1) << 1) | in __spm_set_power_control()
312 (((u32)pwrctrl->reg_img_ddren_rmb & 0x1) << 2) | in __spm_set_power_control()
313 (((u32)pwrctrl->reg_img_emi_rmb & 0x1) << 3) | in __spm_set_power_control()
314 (((u32)pwrctrl->reg_img_infra_rmb & 0x1) << 4) | in __spm_set_power_control()
315 (((u32)pwrctrl->reg_img_pmic_rmb & 0x1) << 5) | in __spm_set_power_control()
316 (((u32)pwrctrl->reg_img_srcclkena_mb & 0x1) << 6) | in __spm_set_power_control()
317 (((u32)pwrctrl->reg_img_vrf18_rmb & 0x1) << 7) | in __spm_set_power_control()
318 (((u32)pwrctrl->reg_infrasys_apsrc_rmb & 0x1) << 8) | in __spm_set_power_control()
319 (((u32)pwrctrl->reg_infrasys_ddren_rmb & 0x1) << 9) | in __spm_set_power_control()
320 (((u32)pwrctrl->reg_infrasys_emi_rmb & 0x1) << 10) | in __spm_set_power_control()
321 (((u32)pwrctrl->reg_infrasys_infra_rmb & 0x1) << 11) | in __spm_set_power_control()
322 (((u32)pwrctrl->reg_infrasys_pmic_rmb & 0x1) << 12) | in __spm_set_power_control()
323 (((u32)pwrctrl->reg_infrasys_srcclkena_mb & 0x1) << 13) | in __spm_set_power_control()
324 (((u32)pwrctrl->reg_infrasys_vcore_rmb & 0x1) << 14) | in __spm_set_power_control()
325 (((u32)pwrctrl->reg_infrasys_vrf18_rmb & 0x1) << 15) | in __spm_set_power_control()
326 (((u32)pwrctrl->reg_ipic_infra_rmb & 0x1) << 16) | in __spm_set_power_control()
327 (((u32)pwrctrl->reg_ipic_vrf18_rmb & 0x1) << 17) | in __spm_set_power_control()
328 (((u32)pwrctrl->reg_mcu_apsrc_rmb & 0x1) << 18) | in __spm_set_power_control()
329 (((u32)pwrctrl->reg_mcu_ddren_rmb & 0x1) << 19) | in __spm_set_power_control()
330 (((u32)pwrctrl->reg_mcu_emi_rmb & 0x1) << 20) | in __spm_set_power_control()
331 (((u32)pwrctrl->reg_mcu_infra_rmb & 0x1) << 21) | in __spm_set_power_control()
332 (((u32)pwrctrl->reg_mcu_pmic_rmb & 0x1) << 22) | in __spm_set_power_control()
333 (((u32)pwrctrl->reg_mcu_srcclkena_mb & 0x1) << 23) | in __spm_set_power_control()
334 (((u32)pwrctrl->reg_mcu_vcore_rmb & 0x1) << 24) | in __spm_set_power_control()
335 (((u32)pwrctrl->reg_mcu_vrf18_rmb & 0x1) << 25) | in __spm_set_power_control()
336 (((u32)pwrctrl->reg_md_apsrc_rmb & 0x1) << 26) | in __spm_set_power_control()
337 (((u32)pwrctrl->reg_md_ddren_rmb & 0x1) << 27) | in __spm_set_power_control()
338 (((u32)pwrctrl->reg_md_emi_rmb & 0x1) << 28) | in __spm_set_power_control()
339 (((u32)pwrctrl->reg_md_infra_rmb & 0x1) << 29) | in __spm_set_power_control()
340 (((u32)pwrctrl->reg_md_pmic_rmb & 0x1) << 30) | in __spm_set_power_control()
341 (((u32)pwrctrl->reg_md_srcclkena_mb & 0x1) << 31)); in __spm_set_power_control()
345 (((u32)pwrctrl->reg_md_srcclkena1_mb & 0x1) << 0) | in __spm_set_power_control()
346 (((u32)pwrctrl->reg_md_vcore_rmb & 0x1) << 1) | in __spm_set_power_control()
347 (((u32)pwrctrl->reg_md_vrf18_rmb & 0x1) << 2) | in __spm_set_power_control()
348 (((u32)pwrctrl->reg_mm_proc_apsrc_rmb & 0x1) << 3) | in __spm_set_power_control()
349 (((u32)pwrctrl->reg_mm_proc_ddren_rmb & 0x1) << 4) | in __spm_set_power_control()
350 (((u32)pwrctrl->reg_mm_proc_emi_rmb & 0x1) << 5) | in __spm_set_power_control()
351 (((u32)pwrctrl->reg_mm_proc_infra_rmb & 0x1) << 6) | in __spm_set_power_control()
352 (((u32)pwrctrl->reg_mm_proc_pmic_rmb & 0x1) << 7) | in __spm_set_power_control()
353 (((u32)pwrctrl->reg_mm_proc_srcclkena_mb & 0x1) << 8) | in __spm_set_power_control()
354 (((u32)pwrctrl->reg_mm_proc_vcore_rmb & 0x1) << 9) | in __spm_set_power_control()
355 (((u32)pwrctrl->reg_mm_proc_vrf18_rmb & 0x1) << 10) | in __spm_set_power_control()
356 (((u32)pwrctrl->reg_mml0_apsrc_rmb & 0x1) << 11) | in __spm_set_power_control()
357 (((u32)pwrctrl->reg_mml0_ddren_rmb & 0x1) << 12) | in __spm_set_power_control()
358 (((u32)pwrctrl->reg_mml0_emi_rmb & 0x1) << 13) | in __spm_set_power_control()
359 (((u32)pwrctrl->reg_mml0_infra_rmb & 0x1) << 14) | in __spm_set_power_control()
360 (((u32)pwrctrl->reg_mml0_pmic_rmb & 0x1) << 15) | in __spm_set_power_control()
361 (((u32)pwrctrl->reg_mml0_srcclkena_mb & 0x1) << 16) | in __spm_set_power_control()
362 (((u32)pwrctrl->reg_mml0_vrf18_rmb & 0x1) << 17) | in __spm_set_power_control()
363 (((u32)pwrctrl->reg_mml1_apsrc_rmb & 0x1) << 18) | in __spm_set_power_control()
364 (((u32)pwrctrl->reg_mml1_ddren_rmb & 0x1) << 19) | in __spm_set_power_control()
365 (((u32)pwrctrl->reg_mml1_emi_rmb & 0x1) << 20) | in __spm_set_power_control()
366 (((u32)pwrctrl->reg_mml1_infra_rmb & 0x1) << 21) | in __spm_set_power_control()
367 (((u32)pwrctrl->reg_mml1_pmic_rmb & 0x1) << 22) | in __spm_set_power_control()
368 (((u32)pwrctrl->reg_mml1_srcclkena_mb & 0x1) << 23) | in __spm_set_power_control()
369 (((u32)pwrctrl->reg_mml1_vrf18_rmb & 0x1) << 24) | in __spm_set_power_control()
370 (((u32)pwrctrl->reg_ovl0_apsrc_rmb & 0x1) << 25) | in __spm_set_power_control()
371 (((u32)pwrctrl->reg_ovl0_ddren_rmb & 0x1) << 26) | in __spm_set_power_control()
372 (((u32)pwrctrl->reg_ovl0_emi_rmb & 0x1) << 27) | in __spm_set_power_control()
373 (((u32)pwrctrl->reg_ovl0_infra_rmb & 0x1) << 28) | in __spm_set_power_control()
374 (((u32)pwrctrl->reg_ovl0_pmic_rmb & 0x1) << 29) | in __spm_set_power_control()
375 (((u32)pwrctrl->reg_ovl0_srcclkena_mb & 0x1) << 30) | in __spm_set_power_control()
376 (((u32)pwrctrl->reg_ovl0_vrf18_rmb & 0x1) << 31)); in __spm_set_power_control()
379 (((u32)pwrctrl->reg_ovl1_apsrc_rmb & 0x1) << 0) | in __spm_set_power_control()
380 (((u32)pwrctrl->reg_ovl1_ddren_rmb & 0x1) << 1) | in __spm_set_power_control()
381 (((u32)pwrctrl->reg_ovl1_emi_rmb & 0x1) << 2) | in __spm_set_power_control()
382 (((u32)pwrctrl->reg_ovl1_infra_rmb & 0x1) << 3) | in __spm_set_power_control()
383 (((u32)pwrctrl->reg_ovl1_pmic_rmb & 0x1) << 4) | in __spm_set_power_control()
384 (((u32)pwrctrl->reg_ovl1_srcclkena_mb & 0x1) << 5) | in __spm_set_power_control()
385 (((u32)pwrctrl->reg_ovl1_vrf18_rmb & 0x1) << 6) | in __spm_set_power_control()
386 (((u32)pwrctrl->reg_pcie0_apsrc_rmb & 0x1) << 7) | in __spm_set_power_control()
387 (((u32)pwrctrl->reg_pcie0_ddren_rmb & 0x1) << 8) | in __spm_set_power_control()
388 (((u32)pwrctrl->reg_pcie0_emi_rmb & 0x1) << 9) | in __spm_set_power_control()
389 (((u32)pwrctrl->reg_pcie0_infra_rmb & 0x1) << 10) | in __spm_set_power_control()
390 (((u32)pwrctrl->reg_pcie0_pmic_rmb & 0x1) << 11) | in __spm_set_power_control()
391 (((u32)pwrctrl->reg_pcie0_srcclkena_mb & 0x1) << 12) | in __spm_set_power_control()
392 (((u32)pwrctrl->reg_pcie0_vcore_rmb & 0x1) << 13) | in __spm_set_power_control()
393 (((u32)pwrctrl->reg_pcie0_vrf18_rmb & 0x1) << 14) | in __spm_set_power_control()
394 (((u32)pwrctrl->reg_pcie1_apsrc_rmb & 0x1) << 15) | in __spm_set_power_control()
395 (((u32)pwrctrl->reg_pcie1_ddren_rmb & 0x1) << 16) | in __spm_set_power_control()
396 (((u32)pwrctrl->reg_pcie1_emi_rmb & 0x1) << 17) | in __spm_set_power_control()
397 (((u32)pwrctrl->reg_pcie1_infra_rmb & 0x1) << 18) | in __spm_set_power_control()
398 (((u32)pwrctrl->reg_pcie1_pmic_rmb & 0x1) << 19) | in __spm_set_power_control()
399 (((u32)pwrctrl->reg_pcie1_srcclkena_mb & 0x1) << 20) | in __spm_set_power_control()
400 (((u32)pwrctrl->reg_pcie1_vcore_rmb & 0x1) << 21) | in __spm_set_power_control()
401 (((u32)pwrctrl->reg_pcie1_vrf18_rmb & 0x1) << 22) | in __spm_set_power_control()
402 (((u32)pwrctrl->reg_perisys_apsrc_rmb & 0x1) << 23) | in __spm_set_power_control()
403 (((u32)pwrctrl->reg_perisys_ddren_rmb & 0x1) << 24) | in __spm_set_power_control()
404 (((u32)pwrctrl->reg_perisys_emi_rmb & 0x1) << 25) | in __spm_set_power_control()
405 (((u32)pwrctrl->reg_perisys_infra_rmb & 0x1) << 26) | in __spm_set_power_control()
406 (((u32)pwrctrl->reg_perisys_pmic_rmb & 0x1) << 27) | in __spm_set_power_control()
407 (((u32)pwrctrl->reg_perisys_srcclkena_mb & 0x1) << 28) | in __spm_set_power_control()
408 (((u32)pwrctrl->reg_perisys_vcore_rmb & 0x1) << 29) | in __spm_set_power_control()
409 (((u32)pwrctrl->reg_perisys_vrf18_rmb & 0x1) << 30) | in __spm_set_power_control()
410 (((u32)pwrctrl->reg_pmsr_apsrc_rmb & 0x1) << 31)); in __spm_set_power_control()
414 (((u32)pwrctrl->reg_pmsr_ddren_rmb & 0x1) << 0) | in __spm_set_power_control()
415 (((u32)pwrctrl->reg_pmsr_emi_rmb & 0x1) << 1) | in __spm_set_power_control()
416 (((u32)pwrctrl->reg_pmsr_infra_rmb & 0x1) << 2) | in __spm_set_power_control()
417 (((u32)pwrctrl->reg_pmsr_pmic_rmb & 0x1) << 3) | in __spm_set_power_control()
418 (((u32)pwrctrl->reg_pmsr_srcclkena_mb & 0x1) << 4) | in __spm_set_power_control()
419 (((u32)pwrctrl->reg_pmsr_vcore_rmb & 0x1) << 5) | in __spm_set_power_control()
420 (((u32)pwrctrl->reg_pmsr_vrf18_rmb & 0x1) << 6) | in __spm_set_power_control()
421 (((u32)pwrctrl->reg_scp_apsrc_rmb & 0x1) << 7) | in __spm_set_power_control()
422 (((u32)pwrctrl->reg_scp_ddren_rmb & 0x1) << 8) | in __spm_set_power_control()
423 (((u32)pwrctrl->reg_scp_emi_rmb & 0x1) << 9) | in __spm_set_power_control()
424 (((u32)pwrctrl->reg_scp_infra_rmb & 0x1) << 10) | in __spm_set_power_control()
425 (((u32)pwrctrl->reg_scp_pmic_rmb & 0x1) << 11) | in __spm_set_power_control()
426 (((u32)pwrctrl->reg_scp_srcclkena_mb & 0x1) << 12) | in __spm_set_power_control()
427 (((u32)pwrctrl->reg_scp_vcore_rmb & 0x1) << 13) | in __spm_set_power_control()
428 (((u32)pwrctrl->reg_scp_vrf18_rmb & 0x1) << 14) | in __spm_set_power_control()
429 (((u32)pwrctrl->reg_spu_hwr_apsrc_rmb & 0x1) << 15) | in __spm_set_power_control()
430 (((u32)pwrctrl->reg_spu_hwr_ddren_rmb & 0x1) << 16) | in __spm_set_power_control()
431 (((u32)pwrctrl->reg_spu_hwr_emi_rmb & 0x1) << 17) | in __spm_set_power_control()
432 (((u32)pwrctrl->reg_spu_hwr_infra_rmb & 0x1) << 18) | in __spm_set_power_control()
433 (((u32)pwrctrl->reg_spu_hwr_pmic_rmb & 0x1) << 19) | in __spm_set_power_control()
434 (((u32)pwrctrl->reg_spu_hwr_srcclkena_mb & 0x1) << 20) | in __spm_set_power_control()
435 (((u32)pwrctrl->reg_spu_hwr_vcore_rmb & 0x1) << 21) | in __spm_set_power_control()
436 (((u32)pwrctrl->reg_spu_hwr_vrf18_rmb & 0x1) << 22) | in __spm_set_power_control()
437 (((u32)pwrctrl->reg_spu_ise_apsrc_rmb & 0x1) << 23) | in __spm_set_power_control()
438 (((u32)pwrctrl->reg_spu_ise_ddren_rmb & 0x1) << 24) | in __spm_set_power_control()
439 (((u32)pwrctrl->reg_spu_ise_emi_rmb & 0x1) << 25) | in __spm_set_power_control()
440 (((u32)pwrctrl->reg_spu_ise_infra_rmb & 0x1) << 26) | in __spm_set_power_control()
441 (((u32)pwrctrl->reg_spu_ise_pmic_rmb & 0x1) << 27) | in __spm_set_power_control()
442 (((u32)pwrctrl->reg_spu_ise_srcclkena_mb & 0x1) << 28) | in __spm_set_power_control()
443 (((u32)pwrctrl->reg_spu_ise_vcore_rmb & 0x1) << 29) | in __spm_set_power_control()
444 (((u32)pwrctrl->reg_spu_ise_vrf18_rmb & 0x1) << 30)); in __spm_set_power_control()
448 (((u32)pwrctrl->reg_srcclkeni_infra_rmb & 0x3) << 0) | in __spm_set_power_control()
449 (((u32)pwrctrl->reg_srcclkeni_pmic_rmb & 0x3) << 2) | in __spm_set_power_control()
450 (((u32)pwrctrl->reg_srcclkeni_srcclkena_mb & 0x3) << 4) | in __spm_set_power_control()
451 (((u32)pwrctrl->reg_srcclkeni_vcore_rmb & 0x3) << 6) | in __spm_set_power_control()
452 (((u32)pwrctrl->reg_sspm_apsrc_rmb & 0x1) << 8) | in __spm_set_power_control()
453 (((u32)pwrctrl->reg_sspm_ddren_rmb & 0x1) << 9) | in __spm_set_power_control()
454 (((u32)pwrctrl->reg_sspm_emi_rmb & 0x1) << 10) | in __spm_set_power_control()
455 (((u32)pwrctrl->reg_sspm_infra_rmb & 0x1) << 11) | in __spm_set_power_control()
456 (((u32)pwrctrl->reg_sspm_pmic_rmb & 0x1) << 12) | in __spm_set_power_control()
457 (((u32)pwrctrl->reg_sspm_srcclkena_mb & 0x1) << 13) | in __spm_set_power_control()
458 (((u32)pwrctrl->reg_sspm_vrf18_rmb & 0x1) << 14) | in __spm_set_power_control()
459 (((u32)pwrctrl->reg_ssrsys_apsrc_rmb & 0x1) << 15) | in __spm_set_power_control()
460 (((u32)pwrctrl->reg_ssrsys_ddren_rmb & 0x1) << 16) | in __spm_set_power_control()
461 (((u32)pwrctrl->reg_ssrsys_emi_rmb & 0x1) << 17) | in __spm_set_power_control()
462 (((u32)pwrctrl->reg_ssrsys_infra_rmb & 0x1) << 18) | in __spm_set_power_control()
463 (((u32)pwrctrl->reg_ssrsys_pmic_rmb & 0x1) << 19) | in __spm_set_power_control()
464 (((u32)pwrctrl->reg_ssrsys_srcclkena_mb & 0x1) << 20) | in __spm_set_power_control()
465 (((u32)pwrctrl->reg_ssrsys_vcore_rmb & 0x1) << 21) | in __spm_set_power_control()
466 (((u32)pwrctrl->reg_ssrsys_vrf18_rmb & 0x1) << 22) | in __spm_set_power_control()
467 (((u32)pwrctrl->reg_ssusb_apsrc_rmb & 0x1) << 23) | in __spm_set_power_control()
468 (((u32)pwrctrl->reg_ssusb_ddren_rmb & 0x1) << 24) | in __spm_set_power_control()
469 (((u32)pwrctrl->reg_ssusb_emi_rmb & 0x1) << 25) | in __spm_set_power_control()
470 (((u32)pwrctrl->reg_ssusb_infra_rmb & 0x1) << 26) | in __spm_set_power_control()
471 (((u32)pwrctrl->reg_ssusb_pmic_rmb & 0x1) << 27) | in __spm_set_power_control()
472 (((u32)pwrctrl->reg_ssusb_srcclkena_mb & 0x1) << 28) | in __spm_set_power_control()
473 (((u32)pwrctrl->reg_ssusb_vcore_rmb & 0x1) << 29) | in __spm_set_power_control()
474 (((u32)pwrctrl->reg_ssusb_vrf18_rmb & 0x1) << 30) | in __spm_set_power_control()
475 (((u32)pwrctrl->reg_uart_hub_infra_rmb & 0x1) << 31)); in __spm_set_power_control()
479 (((u32)pwrctrl->reg_uart_hub_pmic_rmb & 0x1) << 0) | in __spm_set_power_control()
480 (((u32)pwrctrl->reg_uart_hub_srcclkena_mb & 0x1) << 1) | in __spm_set_power_control()
481 (((u32)pwrctrl->reg_uart_hub_vcore_rmb & 0x1) << 2) | in __spm_set_power_control()
482 (((u32)pwrctrl->reg_uart_hub_vrf18_rmb & 0x1) << 3) | in __spm_set_power_control()
483 (((u32)pwrctrl->reg_ufs_apsrc_rmb & 0x1) << 4) | in __spm_set_power_control()
484 (((u32)pwrctrl->reg_ufs_ddren_rmb & 0x1) << 5) | in __spm_set_power_control()
485 (((u32)pwrctrl->reg_ufs_emi_rmb & 0x1) << 6) | in __spm_set_power_control()
486 (((u32)pwrctrl->reg_ufs_infra_rmb & 0x1) << 7) | in __spm_set_power_control()
487 (((u32)pwrctrl->reg_ufs_pmic_rmb & 0x1) << 8) | in __spm_set_power_control()
488 (((u32)pwrctrl->reg_ufs_srcclkena_mb & 0x1) << 9) | in __spm_set_power_control()
489 (((u32)pwrctrl->reg_ufs_vcore_rmb & 0x1) << 10) | in __spm_set_power_control()
490 (((u32)pwrctrl->reg_ufs_vrf18_rmb & 0x1) << 11) | in __spm_set_power_control()
491 (((u32)pwrctrl->reg_vdec_apsrc_rmb & 0x1) << 12) | in __spm_set_power_control()
492 (((u32)pwrctrl->reg_vdec_ddren_rmb & 0x1) << 13) | in __spm_set_power_control()
493 (((u32)pwrctrl->reg_vdec_emi_rmb & 0x1) << 14) | in __spm_set_power_control()
494 (((u32)pwrctrl->reg_vdec_infra_rmb & 0x1) << 15) | in __spm_set_power_control()
495 (((u32)pwrctrl->reg_vdec_pmic_rmb & 0x1) << 16) | in __spm_set_power_control()
496 (((u32)pwrctrl->reg_vdec_srcclkena_mb & 0x1) << 17) | in __spm_set_power_control()
497 (((u32)pwrctrl->reg_vdec_vrf18_rmb & 0x1) << 18) | in __spm_set_power_control()
498 (((u32)pwrctrl->reg_venc_apsrc_rmb & 0x1) << 19) | in __spm_set_power_control()
499 (((u32)pwrctrl->reg_venc_ddren_rmb & 0x1) << 20) | in __spm_set_power_control()
500 (((u32)pwrctrl->reg_venc_emi_rmb & 0x1) << 21) | in __spm_set_power_control()
501 (((u32)pwrctrl->reg_venc_infra_rmb & 0x1) << 22) | in __spm_set_power_control()
502 (((u32)pwrctrl->reg_venc_pmic_rmb & 0x1) << 23) | in __spm_set_power_control()
503 (((u32)pwrctrl->reg_venc_srcclkena_mb & 0x1) << 24) | in __spm_set_power_control()
504 (((u32)pwrctrl->reg_venc_vrf18_rmb & 0x1) << 25) | in __spm_set_power_control()
505 (((u32)pwrctrl->reg_vlpcfg_apsrc_rmb & 0x1) << 26) | in __spm_set_power_control()
506 (((u32)pwrctrl->reg_vlpcfg_ddren_rmb & 0x1) << 27) | in __spm_set_power_control()
507 (((u32)pwrctrl->reg_vlpcfg_emi_rmb & 0x1) << 28) | in __spm_set_power_control()
508 (((u32)pwrctrl->reg_vlpcfg_infra_rmb & 0x1) << 29) | in __spm_set_power_control()
509 (((u32)pwrctrl->reg_vlpcfg_pmic_rmb & 0x1) << 30) | in __spm_set_power_control()
510 (((u32)pwrctrl->reg_vlpcfg_srcclkena_mb & 0x1) << 31)); in __spm_set_power_control()
514 (((u32)pwrctrl->reg_vlpcfg_vcore_rmb & 0x1) << 0) | in __spm_set_power_control()
515 (((u32)pwrctrl->reg_vlpcfg_vrf18_rmb & 0x1) << 1) | in __spm_set_power_control()
516 (((u32)pwrctrl->reg_vlpcfg1_apsrc_rmb & 0x1) << 2) | in __spm_set_power_control()
517 (((u32)pwrctrl->reg_vlpcfg1_ddren_rmb & 0x1) << 3) | in __spm_set_power_control()
518 (((u32)pwrctrl->reg_vlpcfg1_emi_rmb & 0x1) << 4) | in __spm_set_power_control()
519 (((u32)pwrctrl->reg_vlpcfg1_infra_rmb & 0x1) << 5) | in __spm_set_power_control()
520 (((u32)pwrctrl->reg_vlpcfg1_pmic_rmb & 0x1) << 6) | in __spm_set_power_control()
521 (((u32)pwrctrl->reg_vlpcfg1_srcclkena_mb & 0x1) << 7) | in __spm_set_power_control()
522 (((u32)pwrctrl->reg_vlpcfg1_vcore_rmb & 0x1) << 8) | in __spm_set_power_control()
523 (((u32)pwrctrl->reg_vlpcfg1_vrf18_rmb & 0x1) << 9)); in __spm_set_power_control()
527 (((u32)pwrctrl->reg_spm_sw_vcore_rmb & 0xffff) << 0) | in __spm_set_power_control()
528 (((u32)pwrctrl->reg_spm_sw_pmic_rmb & 0xffff) << 16)); in __spm_set_power_control()
532 (((u32)pwrctrl->reg_spm_sw_srcclkena_mb & 0xffff) << 0)); in __spm_set_power_control()
536 (((u32)pwrctrl->reg_srcclken_fast_resp & 0x1) << 0) | in __spm_set_power_control()
537 (((u32)pwrctrl->reg_csyspwrup_ack_mask & 0x1) << 1)); in __spm_set_power_control()
541 (((u32)pwrctrl->reg_wake_mask & 0xffffffff) << 0)); in __spm_set_power_control()
545 (((u32)pwrctrl->reg_ext_wake_mask & 0xffffffff) << 0)); in __spm_set_power_control()
614 void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) in __spm_set_wakeup_event() argument
623 if (pwrctrl->timer_val_cust == 0) in __spm_set_wakeup_event()
624 val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX; in __spm_set_wakeup_event()
626 val = pwrctrl->timer_val_cust; in __spm_set_wakeup_event()
632 if (pwrctrl->wake_src_cust == 0) in __spm_set_wakeup_event()
633 mask = pwrctrl->wake_src; in __spm_set_wakeup_event()
635 mask = pwrctrl->wake_src_cust; in __spm_set_wakeup_event()
637 if (pwrctrl->reg_csyspwrup_ack_mask) in __spm_set_wakeup_event()
650 void __spm_set_fw_resume_option(struct pwr_ctrl *pwrctrl) in __spm_set_fw_resume_option() argument
655 pwrctrl->pcm_flags1 |= SPM_FLAG1_DISABLE_NO_RESUME; in __spm_set_fw_resume_option()
659 void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl) in __spm_set_pcm_flags() argument
662 if (pwrctrl->pcm_flags_cust_clr != 0) in __spm_set_pcm_flags()
663 pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr; in __spm_set_pcm_flags()
664 if (pwrctrl->pcm_flags_cust_set != 0) in __spm_set_pcm_flags()
665 pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set; in __spm_set_pcm_flags()
666 if (pwrctrl->pcm_flags1_cust_clr != 0) in __spm_set_pcm_flags()
667 pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr; in __spm_set_pcm_flags()
668 if (pwrctrl->pcm_flags1_cust_set != 0) in __spm_set_pcm_flags()
669 pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set; in __spm_set_pcm_flags()
671 mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags); in __spm_set_pcm_flags()
673 mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1); in __spm_set_pcm_flags()
675 mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags); in __spm_set_pcm_flags()
677 mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1); in __spm_set_pcm_flags()
680 void __spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl) in __spm_kick_pcm_to_run() argument
686 __spm_set_pcm_flags(pwrctrl); in __spm_kick_pcm_to_run()