180 void __spm_set_power_control(const struct pwr_ctrl *pwrctrl,  in __spm_set_power_control()  argument
187 		((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 0) |  in __spm_set_power_control()
188 		(((pwrctrl->reg_spm_apsrc_req |  in __spm_set_power_control()
190 		(((pwrctrl->reg_spm_ddren_req |  in __spm_set_power_control()
192 		((pwrctrl->reg_spm_dvfs_req & 0x1) << 3) |  in __spm_set_power_control()
193 		(((pwrctrl->reg_spm_emi_req |  in __spm_set_power_control()
195 		(((pwrctrl->reg_spm_f26m_req |  in __spm_set_power_control()
197 		(((pwrctrl->reg_spm_infra_req |  in __spm_set_power_control()
199 		(((pwrctrl->reg_spm_pmic_req |  in __spm_set_power_control()
201 		(((uint32_t)pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 8) |  in __spm_set_power_control()
202 		(((uint32_t)pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 9) |  in __spm_set_power_control()
203 		(((uint32_t)pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 10) |  in __spm_set_power_control()
204 		((((uint32_t)pwrctrl->reg_spm_vcore_req |  in __spm_set_power_control()
206 		((((uint32_t)pwrctrl->reg_spm_vrf18_req |  in __spm_set_power_control()
208 		(((uint32_t)pwrctrl->adsp_mailbox_state & 0x1) << 16) |  in __spm_set_power_control()
209 		(((uint32_t)pwrctrl->apsrc_state & 0x1) << 17) |  in __spm_set_power_control()
210 		(((uint32_t)pwrctrl->ddren_state & 0x1) << 18) |  in __spm_set_power_control()
211 		(((uint32_t)pwrctrl->dvfs_state & 0x1) << 19) |  in __spm_set_power_control()
212 		(((uint32_t)pwrctrl->emi_state & 0x1) << 20) |  in __spm_set_power_control()
213 		(((uint32_t)pwrctrl->f26m_state & 0x1) << 21) |  in __spm_set_power_control()
214 		(((uint32_t)pwrctrl->infra_state & 0x1) << 22) |  in __spm_set_power_control()
215 		(((uint32_t)pwrctrl->pmic_state & 0x1) << 23) |  in __spm_set_power_control()
216 		(((uint32_t)pwrctrl->scp_mailbox_state & 0x1) << 24) |  in __spm_set_power_control()
217 		(((uint32_t)pwrctrl->sspm_mailbox_state & 0x1) << 25) |  in __spm_set_power_control()
218 		(((uint32_t)pwrctrl->sw_mailbox_state & 0x1) << 26) |  in __spm_set_power_control()
219 		(((uint32_t)pwrctrl->vcore_state & 0x1) << 27) |  in __spm_set_power_control()
220 		(((uint32_t)pwrctrl->vrf18_state & 0x1) << 28));  in __spm_set_power_control()
224 		(((uint32_t)pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 0) |  in __spm_set_power_control()
225 		(((uint32_t)pwrctrl->reg_apu_ddren_req_mask_b & 0x1) << 1) |  in __spm_set_power_control()
226 		(((uint32_t)pwrctrl->reg_apu_emi_req_mask_b & 0x1) << 2) |  in __spm_set_power_control()
227 		(((uint32_t)pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 3) |  in __spm_set_power_control()
228 		(((uint32_t)pwrctrl->reg_apu_pmic_req_mask_b & 0x1) << 4) |  in __spm_set_power_control()
229 		(((uint32_t)pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 5) |  in __spm_set_power_control()
230 		(((uint32_t)pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 6) |  in __spm_set_power_control()
231 		(((uint32_t)pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) |  in __spm_set_power_control()
232 		(((uint32_t)pwrctrl->reg_audio_dsp_ddren_req_mask_b & 0x1) << 8) |  in __spm_set_power_control()
233 		(((uint32_t)pwrctrl->reg_audio_dsp_emi_req_mask_b & 0x1) << 9) |  in __spm_set_power_control()
234 		(((uint32_t)pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 10) |  in __spm_set_power_control()
235 		(((uint32_t)pwrctrl->reg_audio_dsp_pmic_req_mask_b & 0x1) << 11) |  in __spm_set_power_control()
236 		(((uint32_t)pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 12) |  in __spm_set_power_control()
237 		(((uint32_t)pwrctrl->reg_audio_dsp_vcore_req_mask_b & 0x1) << 13) |  in __spm_set_power_control()
238 		(((uint32_t)pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 14) |  in __spm_set_power_control()
239 		(((uint32_t)pwrctrl->reg_cam_apsrc_req_mask_b & 0x1) << 15) |  in __spm_set_power_control()
240 		(((uint32_t)pwrctrl->reg_cam_ddren_req_mask_b & 0x1) << 16) |  in __spm_set_power_control()
241 		(((uint32_t)pwrctrl->reg_cam_emi_req_mask_b & 0x1) << 17) |  in __spm_set_power_control()
242 		(((uint32_t)pwrctrl->reg_cam_infra_req_mask_b & 0x1) << 18) |  in __spm_set_power_control()
243 		(((uint32_t)pwrctrl->reg_cam_pmic_req_mask_b & 0x1) << 19) |  in __spm_set_power_control()
244 		(((uint32_t)pwrctrl->reg_cam_srcclkena_mask_b & 0x1) << 20) |  in __spm_set_power_control()
245 		(((uint32_t)pwrctrl->reg_cam_vrf18_req_mask_b & 0x1) << 21) |  in __spm_set_power_control()
246 		(((uint32_t)pwrctrl->reg_mdp_emi_req_mask_b & 0x1) << 22));  in __spm_set_power_control()
250 		(((uint32_t)pwrctrl->reg_ccif_apsrc_req_mask_b & 0xfff) << 0) |  in __spm_set_power_control()
251 		(((uint32_t)pwrctrl->reg_ccif_emi_req_mask_b & 0xfff) << 12));  in __spm_set_power_control()
255 		(((uint32_t)pwrctrl->reg_ccif_infra_req_mask_b & 0xfff) << 0) |  in __spm_set_power_control()
256 		(((uint32_t)pwrctrl->reg_ccif_pmic_req_mask_b & 0xfff) << 12));  in __spm_set_power_control()
260 		(((uint32_t)pwrctrl->reg_ccif_srcclkena_mask_b & 0xfff) << 0) |  in __spm_set_power_control()
261 		(((uint32_t)pwrctrl->reg_ccif_vrf18_req_mask_b & 0xfff) << 12) |  in __spm_set_power_control()
262 		(((uint32_t)pwrctrl->reg_ccu_apsrc_req_mask_b & 0x1) << 24) |  in __spm_set_power_control()
263 		(((uint32_t)pwrctrl->reg_ccu_ddren_req_mask_b & 0x1) << 25) |  in __spm_set_power_control()
264 		(((uint32_t)pwrctrl->reg_ccu_emi_req_mask_b & 0x1) << 26) |  in __spm_set_power_control()
265 		(((uint32_t)pwrctrl->reg_ccu_infra_req_mask_b & 0x1) << 27) |  in __spm_set_power_control()
266 		(((uint32_t)pwrctrl->reg_ccu_pmic_req_mask_b & 0x1) << 28) |  in __spm_set_power_control()
267 		(((uint32_t)pwrctrl->reg_ccu_srcclkena_mask_b & 0x1) << 29) |  in __spm_set_power_control()
268 		(((uint32_t)pwrctrl->reg_ccu_vrf18_req_mask_b & 0x1) << 30) |  in __spm_set_power_control()
269 		(((uint32_t)pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 31));  in __spm_set_power_control()
273 		(((uint32_t)pwrctrl->reg_cg_check_ddren_req_mask_b & 0x1) << 0) |  in __spm_set_power_control()
274 		(((uint32_t)pwrctrl->reg_cg_check_emi_req_mask_b & 0x1) << 1) |  in __spm_set_power_control()
275 		(((uint32_t)pwrctrl->reg_cg_check_infra_req_mask_b & 0x1) << 2) |  in __spm_set_power_control()
276 		(((uint32_t)pwrctrl->reg_cg_check_pmic_req_mask_b & 0x1) << 3) |  in __spm_set_power_control()
277 		(((uint32_t)pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 4) |  in __spm_set_power_control()
278 		(((uint32_t)pwrctrl->reg_cg_check_vcore_req_mask_b & 0x1) << 5) |  in __spm_set_power_control()
279 		(((uint32_t)pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 6) |  in __spm_set_power_control()
280 		(((uint32_t)pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 7) |  in __spm_set_power_control()
281 		(((uint32_t)pwrctrl->reg_conn_ddren_req_mask_b & 0x1) << 8) |  in __spm_set_power_control()
282 		(((uint32_t)pwrctrl->reg_conn_emi_req_mask_b & 0x1) << 9) |  in __spm_set_power_control()
283 		(((uint32_t)pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 10) |  in __spm_set_power_control()
284 		(((uint32_t)pwrctrl->reg_conn_pmic_req_mask_b & 0x1) << 11) |  in __spm_set_power_control()
285 		(((uint32_t)pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 12) |  in __spm_set_power_control()
286 		(((uint32_t)pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 13) |  in __spm_set_power_control()
287 		(((uint32_t)pwrctrl->reg_conn_vcore_req_mask_b & 0x1) << 14) |  in __spm_set_power_control()
288 		(((uint32_t)pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 15) |  in __spm_set_power_control()
289 		(((uint32_t)pwrctrl->reg_cpueb_apsrc_req_mask_b & 0x1) << 16) |  in __spm_set_power_control()
290 		(((uint32_t)pwrctrl->reg_cpueb_ddren_req_mask_b & 0x1) << 17) |  in __spm_set_power_control()
291 		(((uint32_t)pwrctrl->reg_cpueb_emi_req_mask_b & 0x1) << 18) |  in __spm_set_power_control()
292 		(((uint32_t)pwrctrl->reg_cpueb_infra_req_mask_b & 0x1) << 19) |  in __spm_set_power_control()
293 		(((uint32_t)pwrctrl->reg_cpueb_pmic_req_mask_b & 0x1) << 20) |  in __spm_set_power_control()
294 		(((uint32_t)pwrctrl->reg_cpueb_srcclkena_mask_b & 0x1) << 21) |  in __spm_set_power_control()
295 		(((uint32_t)pwrctrl->reg_cpueb_vrf18_req_mask_b & 0x1) << 22) |  in __spm_set_power_control()
296 		(((uint32_t)pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 23) |  in __spm_set_power_control()
297 		(((uint32_t)pwrctrl->reg_disp0_ddren_req_mask_b & 0x1) << 24) |  in __spm_set_power_control()
298 		(((uint32_t)pwrctrl->reg_disp0_emi_req_mask_b & 0x1) << 25) |  in __spm_set_power_control()
299 		(((uint32_t)pwrctrl->reg_disp0_infra_req_mask_b & 0x1) << 26) |  in __spm_set_power_control()
300 		(((uint32_t)pwrctrl->reg_disp0_pmic_req_mask_b & 0x1) << 27) |  in __spm_set_power_control()
301 		(((uint32_t)pwrctrl->reg_disp0_srcclkena_mask_b & 0x1) << 28) |  in __spm_set_power_control()
302 		(((uint32_t)pwrctrl->reg_disp0_vrf18_req_mask_b & 0x1) << 29) |  in __spm_set_power_control()
303 		(((uint32_t)pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 30) |  in __spm_set_power_control()
304 		(((uint32_t)pwrctrl->reg_disp1_ddren_req_mask_b & 0x1) << 31));  in __spm_set_power_control()
308 		(((uint32_t)pwrctrl->reg_disp1_emi_req_mask_b & 0x1) << 0) |  in __spm_set_power_control()
309 		(((uint32_t)pwrctrl->reg_disp1_infra_req_mask_b & 0x1) << 1) |  in __spm_set_power_control()
310 		(((uint32_t)pwrctrl->reg_disp1_pmic_req_mask_b & 0x1) << 2) |  in __spm_set_power_control()
311 		(((uint32_t)pwrctrl->reg_disp1_srcclkena_mask_b & 0x1) << 3) |  in __spm_set_power_control()
312 		(((uint32_t)pwrctrl->reg_disp1_vrf18_req_mask_b & 0x1) << 4) |  in __spm_set_power_control()
313 		(((uint32_t)pwrctrl->reg_dpm_apsrc_req_mask_b & 0xf) << 5) |  in __spm_set_power_control()
314 		(((uint32_t)pwrctrl->reg_dpm_ddren_req_mask_b & 0xf) << 9) |  in __spm_set_power_control()
315 		(((uint32_t)pwrctrl->reg_dpm_emi_req_mask_b & 0xf) << 13) |  in __spm_set_power_control()
316 		(((uint32_t)pwrctrl->reg_dpm_infra_req_mask_b & 0xf) << 17) |  in __spm_set_power_control()
317 		(((uint32_t)pwrctrl->reg_dpm_pmic_req_mask_b & 0xf) << 21) |  in __spm_set_power_control()
318 		(((uint32_t)pwrctrl->reg_dpm_srcclkena_mask_b & 0xf) << 25));  in __spm_set_power_control()
322 		(((uint32_t)pwrctrl->reg_dpm_vcore_req_mask_b & 0xf) << 0) |  in __spm_set_power_control()
323 		(((uint32_t)pwrctrl->reg_dpm_vrf18_req_mask_b & 0xf) << 4) |  in __spm_set_power_control()
324 		(((uint32_t)pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 8) |  in __spm_set_power_control()
325 		(((uint32_t)pwrctrl->reg_dpmaif_ddren_req_mask_b & 0x1) << 9) |  in __spm_set_power_control()
326 		(((uint32_t)pwrctrl->reg_dpmaif_emi_req_mask_b & 0x1) << 10) |  in __spm_set_power_control()
327 		(((uint32_t)pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 11) |  in __spm_set_power_control()
328 		(((uint32_t)pwrctrl->reg_dpmaif_pmic_req_mask_b & 0x1) << 12) |  in __spm_set_power_control()
329 		(((uint32_t)pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 13) |  in __spm_set_power_control()
330 		(((uint32_t)pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 14) |  in __spm_set_power_control()
331 		(((uint32_t)pwrctrl->reg_dvfsrc_level_req_mask_b & 0x1) << 15) |  in __spm_set_power_control()
332 		(((uint32_t)pwrctrl->reg_emisys_apsrc_req_mask_b & 0x1) << 16) |  in __spm_set_power_control()
333 		(((uint32_t)pwrctrl->reg_emisys_ddren_req_mask_b & 0x1) << 17) |  in __spm_set_power_control()
334 		(((uint32_t)pwrctrl->reg_emisys_emi_req_mask_b & 0x1) << 18) |  in __spm_set_power_control()
335 		(((uint32_t)pwrctrl->reg_gce_d_apsrc_req_mask_b & 0x1) << 19) |  in __spm_set_power_control()
336 		(((uint32_t)pwrctrl->reg_gce_d_ddren_req_mask_b & 0x1) << 20) |  in __spm_set_power_control()
337 		(((uint32_t)pwrctrl->reg_gce_d_emi_req_mask_b & 0x1) << 21) |  in __spm_set_power_control()
338 		(((uint32_t)pwrctrl->reg_gce_d_infra_req_mask_b & 0x1) << 22) |  in __spm_set_power_control()
339 		(((uint32_t)pwrctrl->reg_gce_d_pmic_req_mask_b & 0x1) << 23) |  in __spm_set_power_control()
340 		(((uint32_t)pwrctrl->reg_gce_d_srcclkena_mask_b & 0x1) << 24) |  in __spm_set_power_control()
341 		(((uint32_t)pwrctrl->reg_gce_d_vrf18_req_mask_b & 0x1) << 25) |  in __spm_set_power_control()
342 		(((uint32_t)pwrctrl->reg_gce_m_apsrc_req_mask_b & 0x1) << 26) |  in __spm_set_power_control()
343 		(((uint32_t)pwrctrl->reg_gce_m_ddren_req_mask_b & 0x1) << 27) |  in __spm_set_power_control()
344 		(((uint32_t)pwrctrl->reg_gce_m_emi_req_mask_b & 0x1) << 28) |  in __spm_set_power_control()
345 		(((uint32_t)pwrctrl->reg_gce_m_infra_req_mask_b & 0x1) << 29) |  in __spm_set_power_control()
346 		(((uint32_t)pwrctrl->reg_gce_m_pmic_req_mask_b & 0x1) << 30) |  in __spm_set_power_control()
347 		(((uint32_t)pwrctrl->reg_gce_m_srcclkena_mask_b & 0x1) << 31));  in __spm_set_power_control()
351 		(((uint32_t)pwrctrl->reg_gce_m_vrf18_req_mask_b & 0x1) << 0) |  in __spm_set_power_control()
352 		(((uint32_t)pwrctrl->reg_gpueb_apsrc_req_mask_b & 0x1) << 1) |  in __spm_set_power_control()
353 		(((uint32_t)pwrctrl->reg_gpueb_ddren_req_mask_b & 0x1) << 2) |  in __spm_set_power_control()
354 		(((uint32_t)pwrctrl->reg_gpueb_emi_req_mask_b & 0x1) << 3) |  in __spm_set_power_control()
355 		(((uint32_t)pwrctrl->reg_gpueb_infra_req_mask_b & 0x1) << 4) |  in __spm_set_power_control()
356 		(((uint32_t)pwrctrl->reg_gpueb_pmic_req_mask_b & 0x1) << 5) |  in __spm_set_power_control()
357 		(((uint32_t)pwrctrl->reg_gpueb_srcclkena_mask_b & 0x1) << 6) |  in __spm_set_power_control()
358 		(((uint32_t)pwrctrl->reg_gpueb_vrf18_req_mask_b & 0x1) << 7) |  in __spm_set_power_control()
359 		(((uint32_t)pwrctrl->reg_hwccf_apsrc_req_mask_b & 0x1) << 8) |  in __spm_set_power_control()
360 		(((uint32_t)pwrctrl->reg_hwccf_ddren_req_mask_b & 0x1) << 9) |  in __spm_set_power_control()
361 		(((uint32_t)pwrctrl->reg_hwccf_emi_req_mask_b & 0x1) << 10) |  in __spm_set_power_control()
362 		(((uint32_t)pwrctrl->reg_hwccf_infra_req_mask_b & 0x1) << 11) |  in __spm_set_power_control()
363 		(((uint32_t)pwrctrl->reg_hwccf_pmic_req_mask_b & 0x1) << 12) |  in __spm_set_power_control()
364 		(((uint32_t)pwrctrl->reg_hwccf_srcclkena_mask_b & 0x1) << 13) |  in __spm_set_power_control()
365 		(((uint32_t)pwrctrl->reg_hwccf_vcore_req_mask_b & 0x1) << 14) |  in __spm_set_power_control()
366 		(((uint32_t)pwrctrl->reg_hwccf_vrf18_req_mask_b & 0x1) << 15) |  in __spm_set_power_control()
367 		(((uint32_t)pwrctrl->reg_img_apsrc_req_mask_b & 0x1) << 16) |  in __spm_set_power_control()
368 		(((uint32_t)pwrctrl->reg_img_ddren_req_mask_b & 0x1) << 17) |  in __spm_set_power_control()
369 		(((uint32_t)pwrctrl->reg_img_emi_req_mask_b & 0x1) << 18) |  in __spm_set_power_control()
370 		(((uint32_t)pwrctrl->reg_img_infra_req_mask_b & 0x1) << 19) |  in __spm_set_power_control()
371 		(((uint32_t)pwrctrl->reg_img_pmic_req_mask_b & 0x1) << 20) |  in __spm_set_power_control()
372 		(((uint32_t)pwrctrl->reg_img_srcclkena_mask_b & 0x1) << 21) |  in __spm_set_power_control()
373 		(((uint32_t)pwrctrl->reg_img_vrf18_req_mask_b & 0x1) << 22) |  in __spm_set_power_control()
374 		(((uint32_t)pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 23) |  in __spm_set_power_control()
375 		(((uint32_t)pwrctrl->reg_infrasys_ddren_req_mask_b & 0x1) << 24) |  in __spm_set_power_control()
376 		(((uint32_t)pwrctrl->reg_infrasys_emi_req_mask_b & 0x1) << 25) |  in __spm_set_power_control()
377 		(((uint32_t)pwrctrl->reg_ipic_infra_req_mask_b & 0x1) << 26) |  in __spm_set_power_control()
378 		(((uint32_t)pwrctrl->reg_ipic_vrf18_req_mask_b & 0x1) << 27) |  in __spm_set_power_control()
379 		(((uint32_t)pwrctrl->reg_mcu_apsrc_req_mask_b & 0x1) << 28) |  in __spm_set_power_control()
380 		(((uint32_t)pwrctrl->reg_mcu_ddren_req_mask_b & 0x1) << 29) |  in __spm_set_power_control()
381 		(((uint32_t)pwrctrl->reg_mcu_emi_req_mask_b & 0x1) << 30));  in __spm_set_power_control()
385 		(((uint32_t)pwrctrl->reg_mcusys_apsrc_req_mask_b & 0xff) << 0) |  in __spm_set_power_control()
386 		(((uint32_t)pwrctrl->reg_mcusys_ddren_req_mask_b & 0xff) << 8) |  in __spm_set_power_control()
387 		(((uint32_t)pwrctrl->reg_mcusys_emi_req_mask_b & 0xff) << 16) |  in __spm_set_power_control()
388 		(((uint32_t)pwrctrl->reg_mcusys_infra_req_mask_b & 0xff) << 24));  in __spm_set_power_control()
392 		(((uint32_t)pwrctrl->reg_mcusys_pmic_req_mask_b & 0xff) << 0) |  in __spm_set_power_control()
393 		(((uint32_t)pwrctrl->reg_mcusys_srcclkena_mask_b & 0xff) << 8) |  in __spm_set_power_control()
394 		(((uint32_t)pwrctrl->reg_mcusys_vrf18_req_mask_b & 0xff) << 16) |  in __spm_set_power_control()
395 		(((uint32_t)pwrctrl->reg_md_apsrc_req_mask_b & 0x1) << 24) |  in __spm_set_power_control()
396 		(((uint32_t)pwrctrl->reg_md_ddren_req_mask_b & 0x1) << 25) |  in __spm_set_power_control()
397 		(((uint32_t)pwrctrl->reg_md_emi_req_mask_b & 0x1) << 26) |  in __spm_set_power_control()
398 		(((uint32_t)pwrctrl->reg_md_infra_req_mask_b & 0x1) << 27) |  in __spm_set_power_control()
399 		(((uint32_t)pwrctrl->reg_md_pmic_req_mask_b & 0x1) << 28) |  in __spm_set_power_control()
400 		(((uint32_t)pwrctrl->reg_md_srcclkena_mask_b & 0x1) << 29) |  in __spm_set_power_control()
401 		(((uint32_t)pwrctrl->reg_md_srcclkena1_mask_b & 0x1) << 30) |  in __spm_set_power_control()
402 		(((uint32_t)pwrctrl->reg_md_vcore_req_mask_b & 0x1) << 31));  in __spm_set_power_control()
406 		(((uint32_t)pwrctrl->reg_md_vrf18_req_mask_b & 0x1) << 0) |  in __spm_set_power_control()
407 		(((uint32_t)pwrctrl->reg_mdp_apsrc_req_mask_b & 0x1) << 1) |  in __spm_set_power_control()
408 		(((uint32_t)pwrctrl->reg_mdp_ddren_req_mask_b & 0x1) << 2) |  in __spm_set_power_control()
409 		(((uint32_t)pwrctrl->reg_mm_proc_apsrc_req_mask_b & 0x1) << 3) |  in __spm_set_power_control()
410 		(((uint32_t)pwrctrl->reg_mm_proc_ddren_req_mask_b & 0x1) << 4) |  in __spm_set_power_control()
411 		(((uint32_t)pwrctrl->reg_mm_proc_emi_req_mask_b & 0x1) << 5) |  in __spm_set_power_control()
412 		(((uint32_t)pwrctrl->reg_mm_proc_infra_req_mask_b & 0x1) << 6) |  in __spm_set_power_control()
413 		(((uint32_t)pwrctrl->reg_mm_proc_pmic_req_mask_b & 0x1) << 7) |  in __spm_set_power_control()
414 		(((uint32_t)pwrctrl->reg_mm_proc_srcclkena_mask_b & 0x1) << 8) |  in __spm_set_power_control()
415 		(((uint32_t)pwrctrl->reg_mm_proc_vrf18_req_mask_b & 0x1) << 9) |  in __spm_set_power_control()
416 		(((uint32_t)pwrctrl->reg_mmsys_apsrc_req_mask_b & 0x1) << 10) |  in __spm_set_power_control()
417 		(((uint32_t)pwrctrl->reg_mmsys_ddren_req_mask_b & 0x1) << 11) |  in __spm_set_power_control()
418 		(((uint32_t)pwrctrl->reg_mmsys_vrf18_req_mask_b & 0x1) << 12) |  in __spm_set_power_control()
419 		(((uint32_t)pwrctrl->reg_pcie0_apsrc_req_mask_b & 0x1) << 13) |  in __spm_set_power_control()
420 		(((uint32_t)pwrctrl->reg_pcie0_ddren_req_mask_b & 0x1) << 14) |  in __spm_set_power_control()
421 		(((uint32_t)pwrctrl->reg_pcie0_infra_req_mask_b & 0x1) << 15) |  in __spm_set_power_control()
422 		(((uint32_t)pwrctrl->reg_pcie0_srcclkena_mask_b & 0x1) << 16) |  in __spm_set_power_control()
423 		(((uint32_t)pwrctrl->reg_pcie0_vrf18_req_mask_b & 0x1) << 17) |  in __spm_set_power_control()
424 		(((uint32_t)pwrctrl->reg_pcie1_apsrc_req_mask_b & 0x1) << 18) |  in __spm_set_power_control()
425 		(((uint32_t)pwrctrl->reg_pcie1_ddren_req_mask_b & 0x1) << 19) |  in __spm_set_power_control()
426 		(((uint32_t)pwrctrl->reg_pcie1_infra_req_mask_b & 0x1) << 20) |  in __spm_set_power_control()
427 		(((uint32_t)pwrctrl->reg_pcie1_srcclkena_mask_b & 0x1) << 21) |  in __spm_set_power_control()
428 		(((uint32_t)pwrctrl->reg_pcie1_vrf18_req_mask_b & 0x1) << 22) |  in __spm_set_power_control()
429 		(((uint32_t)pwrctrl->reg_perisys_apsrc_req_mask_b & 0x1) << 23) |  in __spm_set_power_control()
430 		(((uint32_t)pwrctrl->reg_perisys_ddren_req_mask_b & 0x1) << 24) |  in __spm_set_power_control()
431 		(((uint32_t)pwrctrl->reg_perisys_emi_req_mask_b & 0x1) << 25) |  in __spm_set_power_control()
432 		(((uint32_t)pwrctrl->reg_perisys_infra_req_mask_b & 0x1) << 26) |  in __spm_set_power_control()
433 		(((uint32_t)pwrctrl->reg_perisys_pmic_req_mask_b & 0x1) << 27) |  in __spm_set_power_control()
434 		(((uint32_t)pwrctrl->reg_perisys_srcclkena_mask_b & 0x1) << 28) |  in __spm_set_power_control()
435 		(((uint32_t)pwrctrl->reg_perisys_vcore_req_mask_b & 0x1) << 29) |  in __spm_set_power_control()
436 		(((uint32_t)pwrctrl->reg_perisys_vrf18_req_mask_b & 0x1) << 30) |  in __spm_set_power_control()
437 		(((uint32_t)pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 31));  in __spm_set_power_control()
441 		(((uint32_t)pwrctrl->reg_scp_ddren_req_mask_b & 0x1) << 0) |  in __spm_set_power_control()
442 		(((uint32_t)pwrctrl->reg_scp_emi_req_mask_b & 0x1) << 1) |  in __spm_set_power_control()
443 		(((uint32_t)pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 2) |  in __spm_set_power_control()
444 		(((uint32_t)pwrctrl->reg_scp_pmic_req_mask_b & 0x1) << 3) |  in __spm_set_power_control()
445 		(((uint32_t)pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 4) |  in __spm_set_power_control()
446 		(((uint32_t)pwrctrl->reg_scp_vcore_req_mask_b & 0x1) << 5) |  in __spm_set_power_control()
447 		(((uint32_t)pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 6) |  in __spm_set_power_control()
448 		(((uint32_t)pwrctrl->reg_srcclkeni_infra_req_mask_b & 0x3) << 7) |  in __spm_set_power_control()
449 		(((uint32_t)pwrctrl->reg_srcclkeni_pmic_req_mask_b & 0x3) << 9) |  in __spm_set_power_control()
450 		(((uint32_t)pwrctrl->reg_srcclkeni_srcclkena_mask_b & 0x3) << 11) |  in __spm_set_power_control()
451 		(((uint32_t)pwrctrl->reg_sspm_apsrc_req_mask_b & 0x1) << 13) |  in __spm_set_power_control()
452 		(((uint32_t)pwrctrl->reg_sspm_ddren_req_mask_b & 0x1) << 14) |  in __spm_set_power_control()
453 		(((uint32_t)pwrctrl->reg_sspm_emi_req_mask_b & 0x1) << 15) |  in __spm_set_power_control()
454 		(((uint32_t)pwrctrl->reg_sspm_infra_req_mask_b & 0x1) << 16) |  in __spm_set_power_control()
455 		(((uint32_t)pwrctrl->reg_sspm_pmic_req_mask_b & 0x1) << 17) |  in __spm_set_power_control()
456 		(((uint32_t)pwrctrl->reg_sspm_srcclkena_mask_b & 0x1) << 18) |  in __spm_set_power_control()
457 		(((uint32_t)pwrctrl->reg_sspm_vrf18_req_mask_b & 0x1) << 19) |  in __spm_set_power_control()
458 		(((uint32_t)pwrctrl->reg_ssr_apsrc_req_mask_b & 0x1) << 20) |  in __spm_set_power_control()
459 		(((uint32_t)pwrctrl->reg_ssr_ddren_req_mask_b & 0x1) << 21) |  in __spm_set_power_control()
460 		(((uint32_t)pwrctrl->reg_ssr_emi_req_mask_b & 0x1) << 22) |  in __spm_set_power_control()
461 		(((uint32_t)pwrctrl->reg_ssr_infra_req_mask_b & 0x1) << 23) |  in __spm_set_power_control()
462 		(((uint32_t)pwrctrl->reg_ssr_pmic_req_mask_b & 0x1) << 24) |  in __spm_set_power_control()
463 		(((uint32_t)pwrctrl->reg_ssr_srcclkena_mask_b & 0x1) << 25) |  in __spm_set_power_control()
464 		(((uint32_t)pwrctrl->reg_ssr_vrf18_req_mask_b & 0x1) << 26) |  in __spm_set_power_control()
465 		(((uint32_t)pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 27) |  in __spm_set_power_control()
466 		(((uint32_t)pwrctrl->reg_ufs_ddren_req_mask_b & 0x1) << 28) |  in __spm_set_power_control()
467 		(((uint32_t)pwrctrl->reg_ufs_emi_req_mask_b & 0x1) << 29) |  in __spm_set_power_control()
468 		(((uint32_t)pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 30) |  in __spm_set_power_control()
469 		(((uint32_t)pwrctrl->reg_ufs_pmic_req_mask_b & 0x1) << 31));  in __spm_set_power_control()
473 		(((uint32_t)pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 0) |  in __spm_set_power_control()
474 		(((uint32_t)pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 1) |  in __spm_set_power_control()
475 		(((uint32_t)pwrctrl->reg_vdec_apsrc_req_mask_b & 0x1) << 2) |  in __spm_set_power_control()
476 		(((uint32_t)pwrctrl->reg_vdec_ddren_req_mask_b & 0x1) << 3) |  in __spm_set_power_control()
477 		(((uint32_t)pwrctrl->reg_vdec_emi_req_mask_b & 0x1) << 4) |  in __spm_set_power_control()
478 		(((uint32_t)pwrctrl->reg_vdec_infra_req_mask_b & 0x1) << 5) |  in __spm_set_power_control()
479 		(((uint32_t)pwrctrl->reg_vdec_pmic_req_mask_b & 0x1) << 6) |  in __spm_set_power_control()
480 		(((uint32_t)pwrctrl->reg_vdec_srcclkena_mask_b & 0x1) << 7) |  in __spm_set_power_control()
481 		(((uint32_t)pwrctrl->reg_vdec_vrf18_req_mask_b & 0x1) << 8) |  in __spm_set_power_control()
482 		(((uint32_t)pwrctrl->reg_venc_apsrc_req_mask_b & 0x1) << 9) |  in __spm_set_power_control()
483 		(((uint32_t)pwrctrl->reg_venc_ddren_req_mask_b & 0x1) << 10) |  in __spm_set_power_control()
484 		(((uint32_t)pwrctrl->reg_venc_emi_req_mask_b & 0x1) << 11) |  in __spm_set_power_control()
485 		(((uint32_t)pwrctrl->reg_venc_infra_req_mask_b & 0x1) << 12) |  in __spm_set_power_control()
486 		(((uint32_t)pwrctrl->reg_venc_pmic_req_mask_b & 0x1) << 13) |  in __spm_set_power_control()
487 		(((uint32_t)pwrctrl->reg_venc_srcclkena_mask_b & 0x1) << 14) |  in __spm_set_power_control()
488 		(((uint32_t)pwrctrl->reg_venc_vrf18_req_mask_b & 0x1) << 15) |  in __spm_set_power_control()
489 		(((uint32_t)pwrctrl->reg_ipe_apsrc_req_mask_b & 0x1) << 16) |  in __spm_set_power_control()
490 		(((uint32_t)pwrctrl->reg_ipe_ddren_req_mask_b & 0x1) << 17) |  in __spm_set_power_control()
491 		(((uint32_t)pwrctrl->reg_ipe_emi_req_mask_b & 0x1) << 18) |  in __spm_set_power_control()
492 		(((uint32_t)pwrctrl->reg_ipe_infra_req_mask_b & 0x1) << 19) |  in __spm_set_power_control()
493 		(((uint32_t)pwrctrl->reg_ipe_pmic_req_mask_b & 0x1) << 20) |  in __spm_set_power_control()
494 		(((uint32_t)pwrctrl->reg_ipe_srcclkena_mask_b & 0x1) << 21) |  in __spm_set_power_control()
495 		(((uint32_t)pwrctrl->reg_ipe_vrf18_req_mask_b & 0x1) << 22) |  in __spm_set_power_control()
496 		(((uint32_t)pwrctrl->reg_ufs_vcore_req_mask_b & 0x1) << 23));  in __spm_set_power_control()
500 		(((uint32_t)pwrctrl->reg_srcclken_fast_resp & 0x1) << 0) |  in __spm_set_power_control()
501 		(((uint32_t)pwrctrl->reg_csyspwrup_ack_mask & 0x1) << 1));  in __spm_set_power_control()
505 		(((uint32_t)pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));  in __spm_set_power_control()
509 		(((uint32_t)pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));  in __spm_set_power_control()
578 void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)  in __spm_set_wakeup_event()  argument
588 	if (pwrctrl->timer_val_cust == 0)  in __spm_set_wakeup_event()
589 		val = pwrctrl->timer_val ? pwrctrl->timer_val :  in __spm_set_wakeup_event()
592 		val = pwrctrl->timer_val_cust;  in __spm_set_wakeup_event()
599 	if (pwrctrl->wake_src_cust == 0)  in __spm_set_wakeup_event()
600 		mask = pwrctrl->wake_src;  in __spm_set_wakeup_event()
602 		mask = pwrctrl->wake_src_cust;  in __spm_set_wakeup_event()
604 	if (pwrctrl->reg_csyspwrup_ack_mask)  in __spm_set_wakeup_event()
619 void __spm_set_fw_resume_option(struct pwr_ctrl *pwrctrl)  in __spm_set_fw_resume_option()  argument
624 	pwrctrl->pcm_flags1 |= SPM_FLAG1_DISABLE_NO_RESUME;  in __spm_set_fw_resume_option()
628 void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl)  in __spm_set_pcm_flags()  argument
632 		(pwrctrl->pcm_flags & ~pwrctrl->pcm_flags_cust_clr) |  in __spm_set_pcm_flags()
633 		pwrctrl->pcm_flags_cust_set;  in __spm_set_pcm_flags()
635 		(pwrctrl->pcm_flags1 & ~pwrctrl->pcm_flags1_cust_clr) |  in __spm_set_pcm_flags()
636 		pwrctrl->pcm_flags1_cust_set;  in __spm_set_pcm_flags()
647 void __spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl)  in __spm_kick_pcm_to_run()  argument
655 	__spm_set_pcm_flags(pwrctrl);  in __spm_kick_pcm_to_run()