Lines Matching refs:reg2
95 uintptr_t reg2; in mt_gpio_set_spec_pull_pupd() local
102 reg2 = reg1 + (gpio_info.base & 0xf0); in mt_gpio_set_spec_pull_pupd()
104 mmio_write_32(reg2 + SET, (1U << bit)); in mt_gpio_set_spec_pull_pupd()
111 mmio_write_32(reg2 + CLR, (1U << bit)); in mt_gpio_set_spec_pull_pupd()
112 mmio_write_32((reg2 + 0x010U) + CLR, (1U << bit)); in mt_gpio_set_spec_pull_pupd()
120 uintptr_t reg2; in mt_gpio_set_pull_pu_pd() local
127 reg2 = reg1 - (gpio_info.base & 0xf0); in mt_gpio_set_pull_pu_pd()
132 mmio_write_32(reg2 + SET, (1U << bit)); in mt_gpio_set_pull_pu_pd()
134 mmio_write_32(reg2 + CLR, (1U << bit)); in mt_gpio_set_pull_pu_pd()
139 mmio_write_32(reg2 + CLR, (1U << bit)); in mt_gpio_set_pull_pu_pd()
159 uintptr_t reg2; in mt_gpio_get_spec_pull_pupd() local
169 reg2 = reg1 + (gpio_info.base & 0xf0); in mt_gpio_get_spec_pull_pupd()
171 r0 = (mmio_read_32(reg2) >> bit) & 1U; in mt_gpio_get_spec_pull_pupd()
172 r1 = (mmio_read_32(reg2 + 0x010) >> bit) & 1U; in mt_gpio_get_spec_pull_pupd()
187 uintptr_t reg2; in mt_gpio_get_pull_pu_pd() local
197 reg2 = reg1 - (gpio_info.base & 0xf0); in mt_gpio_get_pull_pu_pd()
199 pd = (mmio_read_32(reg2) >> bit) & 1U; in mt_gpio_get_pull_pu_pd()