Lines Matching refs:reg1
94 uintptr_t reg1; in mt_gpio_set_spec_pull_pupd() local
101 reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset; in mt_gpio_set_spec_pull_pupd()
102 reg2 = reg1 + (gpio_info.base & 0xf0); in mt_gpio_set_spec_pull_pupd()
106 mmio_write_32(reg1 + SET, (1U << bit)); in mt_gpio_set_spec_pull_pupd()
108 mmio_write_32(reg1 + CLR, (1U << bit)); in mt_gpio_set_spec_pull_pupd()
119 uintptr_t reg1; in mt_gpio_set_pull_pu_pd() local
126 reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset; in mt_gpio_set_pull_pu_pd()
127 reg2 = reg1 - (gpio_info.base & 0xf0); in mt_gpio_set_pull_pu_pd()
131 mmio_write_32(reg1 + CLR, (1U << bit)); in mt_gpio_set_pull_pu_pd()
135 mmio_write_32(reg1 + SET, (1U << bit)); in mt_gpio_set_pull_pu_pd()
138 mmio_write_32(reg1 + CLR, (1U << bit)); in mt_gpio_set_pull_pu_pd()
158 uintptr_t reg1; in mt_gpio_get_spec_pull_pupd() local
168 reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset; in mt_gpio_get_spec_pull_pupd()
169 reg2 = reg1 + (gpio_info.base & 0xf0); in mt_gpio_get_spec_pull_pupd()
176 if (mmio_read_32(reg1) & (1U << bit)) { in mt_gpio_get_spec_pull_pupd()
186 uintptr_t reg1; in mt_gpio_get_pull_pu_pd() local
196 reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset; in mt_gpio_get_pull_pu_pd()
197 reg2 = reg1 - (gpio_info.base & 0xf0); in mt_gpio_get_pull_pu_pd()
198 pu = (mmio_read_32(reg1) >> bit) & 1U; in mt_gpio_get_pull_pu_pd()