494 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval)  argument
500 	*retval = mmio_read_32(reg_addr);
506 				uint32_t *retval)  argument
522 	return intel_secure_reg_read(reg_addr, retval);
526 				 uint32_t val, uint32_t *retval)  argument
528 	if (!intel_secure_reg_read(reg_addr, retval)) {
529 		*retval &= ~mask;
530 		*retval |= val & mask;
531 		return intel_secure_reg_write(reg_addr, *retval, retval);
611 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval)  argument
613 	if (mailbox_hwmon_readtemp(chan, retval) < 0) {
620 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval)  argument
622 	if (mailbox_hwmon_readvolt(chan, retval) < 0) {
1941 	uint32_t retval = 0, completed_addr[3];  local
1977 							&retval, &rcv_id);
1978 		switch (retval) {
2003 		status = intel_secure_reg_read(x1, &retval);
2004 		SMC_RET3(handle, status, retval, x1);
2007 		status = intel_secure_reg_write(x1, (uint32_t)x2, &retval);
2008 		SMC_RET3(handle, status, retval, x1);
2012 						 (uint32_t)x3, &retval);
2013 		SMC_RET3(handle, status, retval, x1);
2035 						ARRAY_SIZE(rsu_respbuf), &retval);
2039 			SMC_RET2(handle, status, retval);
2089 		status = intel_smc_fw_version(&retval);
2090 		SMC_RET2(handle, status, retval);
2100 		status = intel_smc_get_usercode(&retval);
2101 		SMC_RET2(handle, status, retval);
2161 		status = intel_hwmon_readtemp(x1, &retval);
2162 		SMC_RET2(handle, status, retval);
2165 		status = intel_hwmon_readvolt(x1, &retval);
2166 		SMC_RET2(handle, status, retval);
2173 		status = intel_fcs_chip_id(&retval, &retval2, &mbox_error);
2174 		SMC_RET4(handle, status, mbox_error, retval, retval2);
2196 		status = intel_fcs_open_crypto_service_session(&retval, &mbox_error);
2197 		SMC_RET3(handle, status, mbox_error, retval);